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/openbmc/linux/drivers/infiniband/sw/rxe/
H A Drxe_mw.c18 struct rxe_mw *mw = to_rmw(ibmw); in rxe_alloc_mw() local
25 ret = rxe_add_to_pool(&rxe->mw_pool, mw); in rxe_alloc_mw()
31 mw->rkey = ibmw->rkey = (mw->elem.index << 8) | rxe_get_next_key(-1); in rxe_alloc_mw()
32 mw->state = (mw->ibmw.type == IB_MW_TYPE_2) ? in rxe_alloc_mw()
34 spin_lock_init(&mw->lock); in rxe_alloc_mw()
36 rxe_finalize(mw); in rxe_alloc_mw()
43 struct rxe_mw *mw = to_rmw(ibmw); in rxe_dealloc_mw() local
45 rxe_cleanup(mw); in rxe_dealloc_mw()
51 struct rxe_mw *mw, struct rxe_mr *mr, int access) in rxe_check_bind_mw() argument
53 if (mw->ibmw.type == IB_MW_TYPE_1) { in rxe_check_bind_mw()
[all …]
H A Drxe.h58 #define rxe_dbg_mw(mw, fmt, ...) ibdev_dbg((mw)->ibmw.device, \ argument
59 "mw#%d %s: " fmt, (mw)->elem.index, __func__, ##__VA_ARGS__)
79 #define rxe_err_mw(mw, fmt, ...) ibdev_err_ratelimited((mw)->ibmw.device, \ argument
80 "mw#%d %s: " fmt, (mw)->elem.index, __func__, ##__VA_ARGS__)
100 #define rxe_info_mw(mw, fmt, ...) ibdev_info_ratelimited((mw)->ibmw.device, \ argument
101 "mw#%d %s: " fmt, (mw)->elem.index, __func__, ##__VA_ARGS__)
/openbmc/u-boot/include/configs/
H A Domap3_cairo.h92 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
93 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
94 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
95 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
96 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
97 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
98 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
99 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
100 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
101 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
[all …]
H A DMPC8610HPCD.h452 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
469 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
482 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
483 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
484 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
485 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
486 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
487 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
488 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
489 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
[all …]
H A DP1010RDB.h747 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
748 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
749 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
750 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
751 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
752 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
756 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
757 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
758 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
759 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
[all …]
H A Dbk4r1.h11 "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
12 "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"
H A DUCP1020.h513 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
517 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
535 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
536 "mw.l 0xffe0f008 0x00400000\0" \
634 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
638 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
653 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
654 "mw.l 0xffe0f008 0x00400000\0" \
719 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
759 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
[all …]
H A Dp1_p2_rdb_pc.h783 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
784 i2c mw 18 3 __SW_BOOT_MASK 1; reset
788 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
789 i2c mw 18 3 __SW_BOOT_MASK 1; reset
793 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
794 i2c mw 18 3 __SW_BOOT_MASK 1; reset
798 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
799 i2c mw 18 3 __SW_BOOT_MASK 1; reset
803 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
804 i2c mw 18 3 __SW_BOOT_MASK 1; reset
[all …]
H A Dtopic_miami.h57 "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
58 "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
/openbmc/linux/drivers/platform/x86/amd/pmf/
H A Dauto-mode.c36 pr_debug("pfloor_perf: %u mW\n", data->mode_set[AUTO_PERFORMANCE].power_floor); in amd_pmf_dump_auto_mode_defaults()
37 pr_debug("pfloor_balanced: %u mW\n", data->mode_set[AUTO_BALANCE].power_floor); in amd_pmf_dump_auto_mode_defaults()
38 pr_debug("pfloor_quiet: %u mW\n", data->mode_set[AUTO_QUIET].power_floor); in amd_pmf_dump_auto_mode_defaults()
41 pr_debug("pd_balanced_to_perf: %u mW\n", in amd_pmf_dump_auto_mode_defaults()
43 pr_debug("pd_perf_to_balanced: %u mW\n", in amd_pmf_dump_auto_mode_defaults()
45 pr_debug("pd_quiet_to_balanced: %u mW\n", in amd_pmf_dump_auto_mode_defaults()
47 pr_debug("pd_balanced_to_quiet: %u mW\n", in amd_pmf_dump_auto_mode_defaults()
56 pr_debug("stt_min_limit_perf_on_lap: %u mW\n", its_mode->power_control.stt_min); in amd_pmf_dump_auto_mode_defaults()
61 pr_debug("stt_min_limit_perf: %u mW\n", its_mode->power_control.stt_min); in amd_pmf_dump_auto_mode_defaults()
66 pr_debug("stt_min_limit_balanced: %u mW\n", its_mode->power_control.stt_min); in amd_pmf_dump_auto_mode_defaults()
[all …]
/openbmc/linux/Documentation/power/powercap/
H A Ddtpm.rst56 SoC (400mW - 3100mW)
58 `-- pkg (400mW - 3100mW)
60 |-- pd0 (100mW - 700mW)
62 `-- pd1 (300mW - 2400mW)
66 SoC (600mW - 5900mW)
68 |-- pkg (400mW - 3100mW)
70 | |-- pd0 (100mW - 700mW)
72 | `-- pd1 (300mW - 2400mW)
74 `-- pd2 (200mW - 2800mW)
90 …dren given their weights. For example, if we set a power limitation of 3200mW at the 'SoC' root no…
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-mmx.py60 def __init__(self, mw): argument
61 if mw not in [0, 32, 64]:
63 self.mw = mw
64 self.ismem = mw != 0
67 return mem_w(self.mw)
95 def __init__(self, rw, mw): argument
98 if mw not in [0, 8, 16, 32, 64]:
101 self.mw = mw
102 self.ismem = mw != 0
105 return mem_w(self.mw)
[all …]
H A Dtest-avx.py96 def __init__(self, reg, mw): argument
97 if mw not in [0, 8, 16, 32, 64, 128, 256]:
100 self.mw = mw
101 self.ismem = mw != 0
104 return mem_w(self.mw)
110 def __init__(self, mw): argument
111 if mw not in [0, 32, 64]:
112 raise Exception("Bad mem width: %s" % mw)
113 self.mw = mw
114 self.ismem = mw != 0
[all …]
/openbmc/linux/net/netfilter/ipvs/
H A Dip_vs_wrr.c28 * - mw: maximum weight
31 * As result, all weights are in the [di..mw] range with a step=di.
33 * First, we start with cw = mw and select dests with weight >= cw.
35 * Last pass should be with cw = di. We have mw/di passes in total:
47 * So, we modify how mw is calculated, now it is reduced with (di - 1),
63 int mw; /* maximum weight */ member
119 mark->mw = ip_vs_wrr_max_weight(svc) - (mark->di - 1); in ip_vs_wrr_init_svc()
120 mark->cw = mark->mw; in ip_vs_wrr_init_svc()
146 mark->mw = ip_vs_wrr_max_weight(svc) - (mark->di - 1); in ip_vs_wrr_dest_changed()
147 if (mark->cw > mark->mw || !mark->cw) in ip_vs_wrr_dest_changed()
[all …]
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PA123 => mw.b ffb00009 1
181 => i2c mw 18 1 f9
182 => i2c mw 18 3 f0
183 => mw.b ffb00011 0
184 => mw.b ffb00017 1
188 => i2c mw 18 1 f1
189 => i2c mw 18 3 f0
190 => mw.b ffb00011 0
191 => mw.b ffb00014 2
192 => mw.b ffb00015 5
[all …]
/openbmc/u-boot/doc/
H A DREADME.b4860qds272 => mw.b ffdf0040 0x30;
273 => mw.b ffdf0010 0x00;
274 => mw.b ffdf0062 0x02;
275 => mw.b ffdf0050 0x02;
276 => mw.b ffdf0010 0x30;
285 => mw.b ffdf0040 0x30
286 => mw.b ffdf0010 0x00
287 => mw.b 0xffdf0050 0x08
288 => mw.b 0xffdf0060 0x82
289 => mw.b ffdf0061 0x00
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/openbmc/linux/drivers/ntb/
H A Dntb_transport.c617 struct ntb_transport_mw *mw; in ntb_transport_setup_qp_mw() local
629 mw = &nt->mw_vec[mw_num]; in ntb_transport_setup_qp_mw()
631 if (!mw->virt_addr) in ntb_transport_setup_qp_mw()
639 rx_size = (unsigned int)mw->xlat_size / num_qps_mw; in ntb_transport_setup_qp_mw()
640 qp->rx_buff = mw->virt_addr + rx_size * (qp_num / mw_count); in ntb_transport_setup_qp_mw()
793 struct ntb_transport_mw *mw = &nt->mw_vec[num_mw]; in ntb_free_mw() local
796 if (!mw->virt_addr) in ntb_free_mw()
800 dma_free_coherent(&pdev->dev, mw->alloc_size, in ntb_free_mw()
801 mw->alloc_addr, mw->dma_addr); in ntb_free_mw()
802 mw->xlat_size = 0; in ntb_free_mw()
[all …]
/openbmc/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_mr.c465 struct hns_roce_mw *mw) in hns_roce_mw_free() argument
470 if (mw->enabled) { in hns_roce_mw_free()
472 key_to_hw_index(mw->rkey) & in hns_roce_mw_free()
475 dev_warn(dev, "MW DESTROY_MPT failed (%d)\n", ret); in hns_roce_mw_free()
478 key_to_hw_index(mw->rkey)); in hns_roce_mw_free()
482 (int)key_to_hw_index(mw->rkey)); in hns_roce_mw_free()
486 struct hns_roce_mw *mw) in hns_roce_mw_enable() argument
491 unsigned long mtpt_idx = key_to_hw_index(mw->rkey); in hns_roce_mw_enable()
505 ret = hr_dev->hw->mw_write_mtpt(mailbox->buf, mw); in hns_roce_mw_enable()
507 dev_err(dev, "MW write mtpt fail!\n"); in hns_roce_mw_enable()
[all …]
/openbmc/openbmc/poky/bitbake/lib/bb/ui/
H A Dncurses.py218 mw = self.MainWindow( main_left, main_top, main_width, main_height )
224 mw.setStatus("Idle")
262 mw.appendText("NOTE: %s\n" % event._message)
264 … mw.appendText(logging.getLevelName(event.levelno) + ': ' + event.getMessage() + '\n')
271 mw.setStatus("Loading Cache: %s [%2d %%]" % ( next(parsespin), x*100/y ) )
273 mw.setStatus("Idle")
274 mw.appendText("Loaded %d entries from dependency cache.\n"
282 mw.setStatus("Parsing Recipes: %s [%2d %%]" % ( next(parsespin), x*100/y ) )
284 mw.setStatus("Idle")
285 mw.appendText("Parsing finished. %d cached, %d parsed, %d skipped, %d masked.\n"
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dmr.c815 struct mlx4_mw *mw) in mlx4_mw_alloc() argument
829 mw->key = hw_index_to_key(index); in mlx4_mw_alloc()
830 mw->pd = pd; in mlx4_mw_alloc()
831 mw->type = type; in mlx4_mw_alloc()
832 mw->enabled = MLX4_MPT_DISABLED; in mlx4_mw_alloc()
838 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw) in mlx4_mw_enable() argument
844 err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mw->key)); in mlx4_mw_enable()
858 mpt_entry->key = cpu_to_be32(key_to_hw_index(mw->key)); in mlx4_mw_enable()
859 mpt_entry->pd_flags = cpu_to_be32(mw->pd); in mlx4_mw_enable()
860 if (mw->type == MLX4_MW_TYPE_2) { in mlx4_mw_enable()
[all …]
/openbmc/linux/include/uapi/linux/
H A Dpsp-dbc.h121 * @PARAM_GET_PWR_CAP: Get socket power cap (mW)
122 * @PARAM_SET_PWR_CAP: Set socket power cap (mW)
128 * @PARAM_GET_SOC_PWR_MAX: Get maximum allowed value for SoC power (mw)
129 * @PARAM_GET_SOC_PWR_MIN: Get minimum allowed value for SoC power (mw)
130 * @PARAM_GET_SOC_PWR_CUR: Get current value for SoC Power (mW)
/openbmc/u-boot/test/py/tests/
H A Dtest_md.py11 using the mw command."""
17 u_boot_console.run_command('mw ' + addr + ' 0 10')
20 u_boot_console.run_command('mw ' + addr + ' ' + val)
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_yellow_carp.h171 uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
175 uint16_t CorePower[8]; //[mW]
184 uint16_t CurrentSocketPower; //[mW]
187 uint32_t ApuPower; //[mW]
188 uint32_t dGpuPower; //[mW]
/openbmc/linux/fs/ocfs2/
H A Ddlmglue.c434 struct ocfs2_mask_waiter *mw, int ret) in ocfs2_update_lock_stats() argument
447 kt = ktime_sub(ktime_get(), mw->mw_lock_start); in ocfs2_update_lock_stats()
474 struct ocfs2_mask_waiter *mw; in ocfs2_track_lock_wait() local
481 mw = list_first_entry(&lockres->l_mask_waiters, in ocfs2_track_lock_wait()
484 ktime_to_us(ktime_mono_to_real(mw->mw_lock_start)); in ocfs2_track_lock_wait()
487 static inline void ocfs2_init_start_time(struct ocfs2_mask_waiter *mw) in ocfs2_init_start_time() argument
489 mw->mw_lock_start = ktime_get(); in ocfs2_init_start_time()
496 int level, struct ocfs2_mask_waiter *mw, int ret) in ocfs2_update_lock_stats() argument
505 static inline void ocfs2_init_start_time(struct ocfs2_mask_waiter *mw) in ocfs2_init_start_time() argument
891 struct ocfs2_mask_waiter *mw, *tmp; in lockres_set_flags() local
[all …]
/openbmc/linux/include/linux/usb/
H A Dpd.h245 #define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
249 #define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) argument
371 #define RDO_BATT_OP_PWR_SHIFT 10 /* 250mW units */
372 #define RDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
374 #define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT) argument
375 #define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT) argument
496 #define PD_P_SNK_STDBY_MW 2500 /* 2500 mW */

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