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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114-roth.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
15 linux,initrd-start = <0x82000000>;
16 linux,initrd-end = <0x82800000>;
24 trusted-foundations {
25 compatible = "tlm,trusted-foundations";
26 tlm,version-major = <2>;
27 tlm,version-minor = <8>;
40 avdd-dsi-csi-supply = <&vdd_1v2_ap>;
[all …]
H A Dtegra114-dalmore.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
34 hdmi-supply = <&vdd_5v0_hdmi>;
35 vdd-supply = <&vdd_hdmi_reg>;
36 pll-supply = <&palmas_smps3_reg>;
38 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
39 nvidia,hpd-gpio =
46 avdd-dsi-csi-supply = <&avdd_1v2_reg>;
[all …]
H A Dtegra30-asus-transformer-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra30-cpu-opp.dtsi"
9 #include "tegra30-cpu-opp-microvolt.dtsi"
12 chassis-type = "convertible";
31 * pre-existing /chosen node to be available to insert the
37 trusted-foundations {
38 compatible = "tlm,trusted-foundations";
[all …]
H A Dtegra124-venice2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
29 vdd-supply = <&vdd_3v3_hdmi>;
30 pll-supply = <&vdd_hdmi_pll>;
31 hdmi-supply = <&vdd_5v0_hdmi>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio =
41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
[all …]
H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
[all …]
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-lpass-lpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
15 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
21 #include "pinctrl-lpass-lpi.h"
36 struct mutex lock; member
44 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_read()
50 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_write()
67 return pctrl->data->nfunctions; in lpi_gpio_get_functions_count()
75 return pctrl->data->functions[function].name; in lpi_gpio_get_function_name()
[all …]
H A Dpinctrl-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
32 #include "../pinctrl-utils.h"
34 #include "pinctrl-msm.h"
41 * struct msm_pinctrl - state for a pinctrl-msm device
49 * @lock: Spinlock to protect register resources as well
72 raw_spinlock_t lock; member
89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
106 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dcirrus,madera.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
30 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
33 pin-settings:
40 '-pins$':
43 - $ref: pincfg-node.yaml#
44 - $ref: pinmux-node.yaml#
63 dmic6, io, dsp-gpio, irq1, irq2, fll1-clk,
[all …]
H A Dnvidia,tegra-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
56 nvidia,pull:
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132-norrin.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
30 vdd-supply = <&vdd_3v3_hdmi>;
31 pll-supply = <&vdd_hdmi_pll>;
32 hdmi-supply = <&vdd_5v0_hdmi>;
34 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
35 nvidia,hpd-gpio =
42 avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>;
[all …]
/openbmc/intel-ipmi-oem/include/
H A Dsmbiosmdrv2.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
41 // ====================== MDR II Pull Command Structures ======================
42 // MDR II Pull Agent status inquiry command
59 // MDR II Pull Agent directory information inquiry command
76 // MDR II Pull Agent data set information inquiry command
94 // MDR II Pull Agent lock data set command
102 // MDR II Pull Agent lock data set response
112 // MDR II Pull Agent unlock data set command
119 // MDR II Pull Agent get data block command
128 // MDR II Pull Agent get data block response
/openbmc/linux/drivers/gpio/
H A Dgpio-mockup.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2015-2016 Bamvor Jian Zhang <bamv2005@gmail.com>
39 * struct gpio_pin_status - structure describing a GPIO status
46 int pull; member
54 struct mutex lock; member
86 return chip->lines[offset].value; in __gpio_mockup_get()
94 mutex_lock(&chip->lock); in gpio_mockup_get()
96 mutex_unlock(&chip->lock); in gpio_mockup_get()
107 mutex_lock(&chip->lock); in gpio_mockup_get_multiple()
108 for_each_set_bit(bit, mask, gc->ngpio) { in gpio_mockup_get_multiple()
[all …]
H A Dgpio-sim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
38 #define GPIO_SIM_NUM_ATTRS 3 /* value, pull and sentinel */
48 struct mutex lock; member
70 gc = &chip->gc; in gpio_sim_apply_pull()
71 desc = &gc->gpiodev->descs[offset]; in gpio_sim_apply_pull()
73 guard(mutex)(&chip->lock); in gpio_sim_apply_pull()
75 if (test_bit(FLAG_REQUESTED, &desc->flags) && in gpio_sim_apply_pull()
76 !test_bit(FLAG_IS_OUT, &desc->flags)) { in gpio_sim_apply_pull()
77 if (value == !!test_bit(offset, chip->value_map)) in gpio_sim_apply_pull()
81 * This is fine - it just means, nobody is listening in gpio_sim_apply_pull()
[all …]
H A Dgpio-wm8994.c1 // SPDX-License-Identifier: GPL-2.0+
33 struct wm8994 *wm8994 = wm8994_gpio->wm8994; in wm8994_gpio_request()
35 switch (wm8994->type) { in wm8994_gpio_request()
43 return -EINVAL; in wm8994_gpio_request()
56 struct wm8994 *wm8994 = wm8994_gpio->wm8994; in wm8994_gpio_direction_in()
65 struct wm8994 *wm8994 = wm8994_gpio->wm8994; in wm8994_gpio_get()
82 struct wm8994 *wm8994 = wm8994_gpio->wm8994; in wm8994_gpio_direction_out()
94 struct wm8994 *wm8994 = wm8994_gpio->wm8994; in wm8994_gpio_set()
106 struct wm8994 *wm8994 = wm8994_gpio->wm8994; in wm8994_gpio_set_config()
120 return -ENOTSUPP; in wm8994_gpio_set_config()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpinmux.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2014
76 /* Defines a pin group cfg's low-power mode select */
82 PMUX_LPMD_NONE = -1,
91 PMUX_SCHMT_NONE = -1,
96 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
100 PMUX_HSM_NONE = -1,
106 * pull up/down settings and tristate settings. Having set up one of these
113 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ member
119 u32 lock:2; /* lock enable/disable PMUX_PIN... */ member
[all …]
/openbmc/linux/drivers/pinctrl/intel/
H A Dpinctrl-lynxpoint.c1 // SPDX-License-Identifier: GPL-2.0
24 #include <linux/pinctrl/pinconf-generic.h>
29 #include "pinctrl-intel.h"
173 #define GPIWP_MASK GENMASK(1, 0) /* weak pull options */
175 #define GPIWP_DOWN 1 /* weak pull down */
176 #define GPIWP_UP 2 /* weak pull up */
189 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
190 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
191 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
206 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
[all …]
/openbmc/linux/include/linux/
H A Dspinlock.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * include/linux/spinlock.h - generic spinlock/rwlock declarations
24 * (also included on UP-debug builds:)
35 * (which is an empty structure on non-debug builds)
44 * builds. (which are NOPs on non-debug, non-preempt
47 * (included on UP-non-debug builds:)
72 #define LOCK_SECTION_NAME ".text..lock."KBUILD_BASENAME
87 * Pull the arch_spinlock_t and arch_rwlock_t definitions:
92 * Pull the arch_spin*() functions/declarations (UP-nondebug doesn't need them):
101 extern void __raw_spin_lock_init(raw_spinlock_t *lock, const char *name,
[all …]
/openbmc/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sunxi.c6 * Maxime Ripard <maxime.ripard@free-electrons.com>
28 #include <linux/pinctrl/pinconf-generic.h>
33 #include <dt-bindings/pinctrl/sun4i-a10.h>
36 #include "pinctrl-sunxi.h"
39 * These lock classes tell lockdep that GPIO IRQs are in a different
51 * - Mux config
52 * - Data value
53 * - Drive level
54 * - Pull direction
67 *reg = bank * pctl->bank_mem_size + MUX_REGS_OFFSET + in sunxi_mux_reg()
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-equilibrium.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define REG_PUEN 0x80 /* PULL UP Enable Register */
12 #define REG_PDEN 0x84 /* PULL DOWN Enable Register */
108 * @lock: spin lock to protect gpio register write.
117 raw_spinlock_t lock; /* protect gpio register */ member
130 * @lock: protect pinctrl register write
141 raw_spinlock_t lock; /* protect pinpad register */ member
/openbmc/linux/drivers/power/supply/
H A Disp1704_charger.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2012 - 2013 Pali Rohár <pali@kernel.org>
63 return usb_phy_io_read(isp->phy, reg); in isp1704_read()
68 return usb_phy_io_write(isp->phy, val, reg); in isp1704_write()
73 gpiod_set_value(isp->enable_gpio, on); in isp1704_charger_set_power()
103 /* Enable strong pull-up on DP (1.5K) and reset */ in isp1704_charger_type()
138 /* Clear the DP and DM pull-down bits */ in isp1704_charger_verify()
142 /* Enable strong pull-up on DP (1.5K) and reset */ in isp1704_charger_verify()
149 /* Disable strong pull-up on DP (1.5K) */ in isp1704_charger_verify()
157 /* Enable weak pull-up resistor on DP */ in isp1704_charger_verify()
[all …]
/openbmc/linux/arch/arm/mach-s3c/
H A Dgpio-cfg-helpers.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Samsung Platform - GPIO pin configuration helper definitions
19 * with the relevant lock held or the system prevented from doing anything else
26 return (chip->config->set_config)(chip, off, config); in samsung_gpio_do_setcfg()
30 unsigned int off, samsung_gpio_pull_t pull) in samsung_gpio_do_setpull() argument
32 return (chip->config->set_pull)(chip, off, pull); in samsung_gpio_do_setpull()
/openbmc/linux/drivers/pwm/
H A Dpwm-iqs620a.c1 // SPDX-License-Identifier: GPL-2.0+
8 * - The period is fixed to 1 ms and is generated continuously despite changes
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
13 * ms, the output is disabled and relies upon an external pull-down resistor
39 struct mutex lock; member
46 struct iqs62x_core *iqs62x = iqs620_pwm->iqs62x; in iqs620_pwm_init()
50 return regmap_clear_bits(iqs62x->regmap, IQS620_PWR_SETTINGS, in iqs620_pwm_init()
53 ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE, in iqs620_pwm_init()
54 duty_scale - 1); in iqs620_pwm_init()
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 /* argument: Integer, range is HW-dependant */
49 /* argument: Integer, range is HW-dependant */
51 /* argument: Integer, range is HW-dependant */
53 /* argument: Integer, range is HW-dependant */
55 /* argument: Integer, range is HW-dependant */
75 * struct tegra_function - Tegra pinctrl mux function
87 * struct tegra_pingroup - Tegra pin group
93 * This register contains the mux, einput, odrain, lock,
97 * @pupd_reg: Pull-up/down register offset.
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/x86/
H A Dtune-i586-nlp.inc1 # Settings for the GCC(1) cpu-type "quark":
5 DEFAULTTUNE ?= "i586-nlp-32"
7 # Include the previous tune to pull in PACKAGE_EXTRA_ARCHS
8 require conf/machine/include/x86/arch-x86.inc
10 # x86 with no lock prefix
11 TUNEVALID[i586-nlp] = "IA32 with Lock Prefix omitted"
12 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'i586-nlp', ' -march=i586 -Wa,-momit-lock-pre…
15 AVAILTUNES = "i586-nlp-32"
16 TUNE_FEATURES:tune-i586-nlp-32 = "${TUNE_FEATURES:tune-x86} i586-nlp"
17 BASE_LIB:tune-i586-nlp-32 = "lib"
[all …]
/openbmc/linux/drivers/pinctrl/bcm/
H A Dpinctrl-iproc-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Broadcom
9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
10 * PINCONF such as bias pull up/down, and drive strength are also supported
30 #include <linux/pinctrl/pinconf-generic.h>
34 #include "../pinctrl-utils.h"
68 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
91 * @lock: lock to protect access to I/O registers
110 raw_spinlock_t lock; member
125 * Mapping from PINCONF pins to GPIO pins is 1-to-1
[all …]

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