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/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclk_synthesizer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * clk-synthesizer.c
7 * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
16 * clk_synthesizer_reg_read - Read register from synthesizer.
58 * clk_synthesizer_reg_write - Write a value to register in synthesizer.
87 * setup_clock_syntherizer - Program the clock synthesizer to get the desired
91 * This is a PLL-based high performance synthesizer which gives 3 outputs
92 * as per the PLL_DIV and load capacitor programmed.
115 if (val != data->id) in setup_clock_synthesizer()
118 /* Crystal Load capacitor selection */ in setup_clock_synthesizer()
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
24 - ti,cdce925
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H A Didt,versaclock5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - 5P49V5923:
17 0 -- OUT0_SEL_I2CB
18 1 -- OUT1
19 2 -- OUT2
21 - 5P49V5933:
22 0 -- OUT0_SEL_I2CB
23 1 -- OUT1
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/openbmc/linux/Documentation/hwmon/
H A Dbel-pfe.rst1 Kernel driver bel-pfe
10 Addresses scanned: -
12 … Datasheet: https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-pfe1100-12-054xa.pdf
18 Addresses scanned: -
20 Datasheet: https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-pfe3000-series.pdf
26 -----------
33 1100 Watt AC to DC power-factor-corrected (PFC) power supply.
38 3000 Watt AC/DC power-factor-corrected (PFC) and DC-DC power supply.
46 -----------
48 This driver does not auto-detect devices. You will have to instantiate the
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_power_init.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
24 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
39 &clkctrl_regs->hw_clkctrl_clkseq_set); in mxs_power_clock2xtal()
43 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
46 * to PLL. This can only be called once the PLL has re-locked and once
63 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, in mxs_power_clock2pll()
71 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, in mxs_power_clock2pll()
76 * mxs_power_set_auto_restart() - Set the auto-restart bit
87 debug("SPL: Setting auto-restart bit\n"); in mxs_power_set_auto_restart()
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/openbmc/linux/drivers/misc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 See Documentation/misc-devices/ad525x_dpot.rst for the
40 module will be called ad525x_dpot-i2c.
51 module will be called ad525x_dpot-spi.
65 This option enables device driver support for in-band access to the
78 website <https://www-03.ibm.com/systems/info/x86servers/serverproven/compat/us/>
189 called smpro-errmon.
199 called smpro-misc.
202 tristate "CS5535/CS5536 Geode Multi-Function General Purpose Timer (MFGPT) support"
209 than the generic PIT, and are suitable for use as high-res timers.
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/openbmc/linux/sound/pci/cs46xx/
H A Dcs46xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include <sound/pcm-indirect.h>
401 * The following defines are for the flags in the PLL capacitor coefficient
464 * The following defines are for the flags in the configuration load 1
475 * The following defines are for the flags in the configuration load 2
1455 * The following define the offsets of the fields within the on-chip generic
1470 * on-chip generic DMA requestor.
1518 * on-chip generic DMA requestor.
1545 * of the on-chip generic DMA requestor.
1560 * on-chip generic DMA requestor.
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/openbmc/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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