| /openbmc/u-boot/drivers/video/ |
| H A D | pwm_backlight.c | 19 * If @num_levels is 0 then the levels are simple values with the backlight
21 * Otherwise the levels are an index into @levels (0..n-1).
28 * @levels: Levels for the backlight, or NULL if not using indexed levels
29 * @num_levels: Number of levels
42 u32 *levels; member
137 if (priv->levels) { in pwm_backlight_set_brightness()
138 level = priv->levels[percent * (priv->num_levels - 1) in pwm_backlight_set_brightness()
207 cell = dev_read_prop(dev, "brightness-levels", &len); in pwm_backlight_ofdata_to_platdata()
210 priv->levels = malloc(len); in pwm_backlight_ofdata_to_platdata()
211 if (!priv->levels) in pwm_backlight_ofdata_to_platdata()
[all …]
|
| /openbmc/qemu/scripts/ |
| H A D | cpu-x86-uarch-abi.py | 6 # compatibility levels for each CPU model.
20 levels = [ variable
113 "levels": [False, False, False, False],
128 for level in range(len(levels)):
130 want = set(levels[level])
135 models[name]["levels"][level] = match
147 for level in range(len(levels)):
148 if models[name]["levels"][level]:
164 if not models[name]["levels"][level]:
174 if not models[name]["levels"][level]:
[all …]
|
| /openbmc/qemu/util/ |
| H A D | hbitmap.c | 22 * that the number of levels is in fact fixed.
25 * granularity; in all levels except the last, bit N is set iff the N-th
44 * Setting or clearing a range of m bits on all levels, the work to perform
95 * Note that all bitmaps have the same number of levels. Even a 1-bit
98 unsigned long *levels[HBITMAP_LEVELS]; member
100 /* The length of each levels[] array. */
117 cur = hbi->cur[i] & hb->levels[i][pos]; in hbitmap_iter_skip_words()
139 cur = hb->levels[i + 1][pos]; in hbitmap_iter_skip_words()
152 hbi->hb->levels[HBITMAP_LEVELS - 1][hbi->pos]; in hbitmap_iter_next()
185 hbi->cur[i] = hb->levels[i][pos] & ~((1UL << bit) - 1); in hbitmap_iter_init()
[all …]
|
| /openbmc/qemu/hw/core/ |
| H A D | or-irq.c | 38 s->levels[n] = level; in or_irq_handler()
41 or_level |= s->levels[i]; in or_irq_handler()
53 s->levels[i] = false; in or_irq_reset()
76 * The subsection migrates as much of the levels[] array as is needed
98 VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0,
109 VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES),
|
| /openbmc/bmcweb/src/ |
| H A D | webserver_cli.cpp | 26 static constexpr std::array<std::string, 7> levels{ variable
33 const std::string* iter = std::ranges::find(levels, input); in validateLogLevel()
34 if (iter == levels.end()) in validateLogLevel()
43 std::string help = "\nLog levels to choose from:\n"; in helpMsg()
44 for (const std::string& prompt : levels) in helpMsg()
|
| /openbmc/qemu/target/riscv/ |
| H A D | monitor.c | 148 int levels, ptidxbits, ptesize, vm, va_bits; in mem_info_svxx() local
166 levels = 2; in mem_info_svxx()
171 levels = 3; in mem_info_svxx()
176 levels = 4; in mem_info_svxx()
181 levels = 5; in mem_info_svxx()
190 va_bits = PGSHIFT + levels * ptidxbits; in mem_info_svxx()
202 walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits, in mem_info_svxx()
|
| /openbmc/phosphor-host-ipmid/user_channel/ |
| H A D | cipher_mgmt.hpp | 52 * privilege levels
55 * levels
65 * suite privilege levels
67 * @param[in] csPrivilegeLevels - cipher suite privilege levels to update
111 /** @brief function to load CS Privilege Levels from json file/files to map
|
| H A D | cipher_mgmt.cpp | 53 lg2::error("CS privilege levels default file does not exist..."); in loadCSPrivilegesToMap()
112 "Corrupted cipher suite privilege levels config file: {ERROR}", in readCSPrivilegeLevels()
182 "Get CS Privilege levels - Invalid channel number: {CHANNEL}", in getCSPrivilegeLevels()
200 "Set CS Privilege levels - Invalid channel number: {CHANNEL}", in setCSPrivilegeLevels()
208 lg2::info("CS privilege levels user settings file does not " in setCSPrivilegeLevels()
240 lg2::error("Error in setting CS Privilege Levels."); in setCSPrivilegeLevels()
|
| /openbmc/qemu/hw/intc/ |
| H A D | heathrow_pic.c | 35 return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask; in heathrow_check_irq()
98 value = pic->levels; in heathrow_read()
124 last_level = (pic->levels & irq_bit) ? 1 : 0; in heathrow_set_irq()
128 pic->levels |= irq_bit; in heathrow_set_irq()
130 pic->levels &= ~irq_bit; in heathrow_set_irq()
147 VMSTATE_UINT32(levels, HeathrowPICState),
|
| /openbmc/qemu/hw/vfio/ |
| H A D | spapr.c | 37 unsigned int levels; member
283 * levels number and if this fails (for example due to the host memory in vfio_spapr_create_window()
284 * fragmentation), we increase levels. The DMA address structure is: in vfio_spapr_create_window()
291 * The aim is to split "x" to smaller possible number of levels. in vfio_spapr_create_window()
304 create.levels = bits_total / bits_per_level; in vfio_spapr_create_window()
306 ddw_levels = scontainer->levels; in vfio_spapr_create_window()
309 ++create.levels; in vfio_spapr_create_window()
312 for ( ; create.levels <= max_levels; ++create.levels) { in vfio_spapr_create_window()
319 if (create.levels > ddw_levels) { in vfio_spapr_create_window()
342 create.levels, in vfio_spapr_create_window()
[all …]
|
| /openbmc/qemu/docs/specs/ |
| H A D | ppc-spapr-numa.rst | 51 the NUMA levels for the platform.
67 three NUMA levels:
77 P2 processors, we would have the following NUMA levels:
150 the distance of the previous level, and the maximum amount of levels is
156 * resources two NUMA levels apart: 40
157 * resources three NUMA levels apart: 80
158 * resources four NUMA levels apart: 160
168 for 4 distinct NUMA distance values based on the NUMA levels
171 NUMA levels, granting user flexibility
|
| /openbmc/u-boot/arch/arm/cpu/armv7/ |
| H A D | cache_v7.c | 104 * at all levels
114 * Invalidates range in all levels of D-cache/unified cache used:
127 * Flush range(clean & invalidate) from all levels of D-cache/unified
|
| /openbmc/phosphor-snmp/ |
| H A D | snmp_serialize.cpp | 31 * a serialized data across code levels
45 * a serialized data across code levels
|
| /openbmc/phosphor-user-manager/phosphor-ldap-config/ |
| H A D | ldap_mapper_serialize.cpp | 27 * across code levels
42 * across code levels
|
| /openbmc/phosphor-dbus-monitor/src/ |
| H A D | event_serialize.cpp | 27 * a serialized data across code levels
41 * a serialized data across code levels
|
| /openbmc/u-boot/arch/arm/include/asm/arch-tegra20/ |
| H A D | pmu.h | 10 /* Set core and CPU voltages to nominal levels */
|
| /openbmc/u-boot/arch/arm/include/asm/arch-tegra30/ |
| H A D | pmu.h | 9 /* Set core and CPU voltages to nominal levels */
|
| /openbmc/u-boot/arch/arm/include/asm/arch-tegra124/ |
| H A D | pmu.h | 10 /* Set core and CPU voltages to nominal levels */
|
| /openbmc/u-boot/arch/arm/include/asm/arch-tegra114/ |
| H A D | pmu.h | 9 /* Set core and CPU voltages to nominal levels */
|
| /openbmc/u-boot/arch/arm/include/asm/arch-tegra210/ |
| H A D | pmu.h | 10 /* Set core and CPU voltages to nominal levels */
|
| /openbmc/bmcweb/test/redfish-core/include/utils/ |
| H A D | query_param_test.cpp | 155 "?$expand=*($levels=2)"); in TEST()
158 "?$expand=~($levels=3)"); in TEST()
161 "?$expand=.($levels=1)"); in TEST()
520 EXPECT_FALSE(getExpandType(".($levels=1", query)); in TEST()
533 EXPECT_TRUE(getExpandType(".($levels=42)", query)); in TEST()
537 EXPECT_FALSE(getExpandType(".($levels=256)", query)); in TEST()
540 EXPECT_FALSE(getExpandType(".($levels=-1)", query)); in TEST()
543 EXPECT_FALSE(getExpandType(".($levels=a)", query)); in TEST()
674 // Previous expand was two levels so we should further expand in TEST()
|
| /openbmc/u-boot/include/linux/ |
| H A D | stringify.h | 4 /* Indirect stringification. Doing two levels allows the parameter to be a
|
| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-bsp/bolt/ |
| H A D | bolt_0.9.6.bb | 2 DESCRIPTION = "Userspace system daemon to enable security levels for Thunderbolt on GNU/Linux"
|
| /openbmc/qemu/docs/system/ |
| H A D | cpu-models-x86.rst.inc | 42 ABI compatibility levels for CPU models
45 The x86_64 architecture has a number of `ABI compatibility levels`_
49 table that follows illustrates which ABI compatibility levels
56 .. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/
58 .. csv-table:: x86-64 ABI compatibility levels
85 Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
|
| /openbmc/bios-settings-mgr/src/ |
| H A D | manager_serialize.cpp | 41 * across code levels
59 * across code levels
|