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/openbmc/linux/Documentation/networking/
H A Dtls-offload-layers.svg1 …l0 720.0l-960.0 0l0 -720.0z" clip-rule="nonzero"/></clipPath><g clip-path="url(#p.0)"><path fill="…
H A Dtls-offload-reorder-good.svg1 …l0 720.0l-960.0 0l0 -720.0z" clip-rule="nonzero"/></clipPath><g clip-path="url(#p.0)"><path fill="…
H A Dtls-offload-reorder-bad.svg1 …l0 720.0l-960.0 0l0 -720.0z" clip-rule="nonzero"/></clipPath><g clip-path="url(#p.0)"><path fill="…
/openbmc/linux/arch/sparc/include/asm/
H A Dhead_32.h13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
38 rd %psr, %l0;
42 rd %psr,%l0; \
50 rd %psr,%l0; \
59 b getcc_trap_handler; rd %psr, %l0; nop; nop;
63 b setcc_trap_handler; rd %psr, %l0; nop; nop;
73 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
[all …]
H A Dxor_32.h28 "ldd [%1 + 0x08], %%l0\n\t" in sparc_2()
33 "xor %%g4, %%l0, %%g4\n\t" in sparc_2()
47 "l0", "l1", "l2", "l3", "l4", "l5"); in sparc_2()
67 "ldd [%1 + 0x08], %%l0\n\t" in sparc_3()
73 "xor %%g4, %%l0, %%g4\n\t" in sparc_3()
75 "ldd [%2 + 0x08], %%l0\n\t" in sparc_3()
84 "xor %%g4, %%l0, %%g4\n\t" in sparc_3()
98 "l0", "l1", "l2", "l3", "l4", "l5"); in sparc_3()
120 "ldd [%1 + 0x08], %%l0\n\t" in sparc_4()
126 "xor %%g4, %%l0, %%g4\n\t" in sparc_4()
[all …]
H A Dttable.h16 rdpr %cleanwin, %l0; add %l0, 1, %l0; \
17 wrpr %l0, 0x0, %cleanwin; \
20 clr %l0; clr %l1; clr %l2; clr %l3; \
252 stx %l0, [%sp + STACK_BIAS + 0x00]; \
273 stx %l0, [%sp + STACK_BIAS + 0x00]; \
299 stxa %l0, [%g1 + %g0] ASI; \
331 stxa %l0, [%sp + STACK_BIAS + 0x00] %asi; \
365 stx %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
395 stwa %l0, [%sp + %g0] ASI; \
430 stwa %l0, [%sp + 0x00] %asi; \
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dentry.S63 * This code cannot touch registers %l0 %l1 and %l2
159 wr %l0, 0x0, %psr
180 or %l0, PSR_PIL, %l4
200 wr %l0, PSR_ET, %psr
229 or %l0, PSR_PIL, %g2
238 or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq
248 or %l0, PSR_PIL, %g2
255 wr %l0, PSR_ET, %psr
286 or %l0, PSR_PIL, %l4
331 or %l0, PSR_PIL, %l4
[all …]
H A Dhvtramp.S47 mov %o0, %l0
49 lduw [%l0 + HVTRAMP_DESCR_CPU], %g1
53 ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2
57 lduw [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2
58 add %l0, HVTRAMP_DESCR_MAPS, %l3
75 ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0
84 ldx [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6
H A Dhead_64.S167 rd %pc, %l0
170 sub %l0, %l1, %l1
185 sub %l0, %l1, %l1
191 sub %l0, %l1, %l1
192 sub %l0, %l2, %l2
193 sub %l0, %l5, %l5
215 sub %l0, %l1, %l1
216 sub %l0, %l2, %l2
217 sub %l0, %l3, %l3
218 stw %l0, [%l3]
[all …]
H A Drtrap_64.S68 mov %l0, %o2
162 ldx [%g6 + TI_FLAGS], %l0
165 andcc %l0, %o0, %g0
169 andcc %l0, _TIF_NEED_RESCHED, %g0
171 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
235 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
238 ldxa [%l7 + %l7] ASI_MMU, %l0
243 or %l0, %l1, %l0
245 661: stxa %l0, [%l7] ASI_DMMU
248 stxa %l0, [%l7] ASI_MMU
H A Dhead_32.S124 mov %o0, %l0 ! stash away romvec
172 /* DON'T TOUCH %l0 thru %l5 in these remapping routines,
363 mov %l0, %o0 ! put back romvec
376 ld [%l1], %l0
377 ld [%l0], %l0
378 call %l0
386 ld [%l1], %l0 ! 'compatible' tells
387 ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where
388 call %l0 ! x is one of 'm', 'd' or 'e'.
731 mov %o4, %l0
[all …]
/openbmc/linux/arch/sparc/lib/
H A Dxor.S370 ldda [%i1 + 0x30] %asi, %l0 /* %l0/%l1 = src + 0x30 */
389 xor %l2, %l0, %l2
418 ldda [%l7 + 0x10] %asi, %l0 /* %l0/%l1 = src2 + 0x10 */
430 xor %l0, %i4, %l0
432 xor %o2, %l0, %o2
437 ldda [%l7 + 0x30] %asi, %l0 /* %l0/%l1 = src2 + 0x30 */
448 xor %l0, %i4, %l0
450 xor %o2, %l0, %o2
482 ldda [%i0 + 0x00] %asi, %l0 /* %l0/%l1 = dest + 0x00 */
489 xor %l0, %g2, %l0
[all …]
H A Dmuldi3.S57 mov %o0, %l0
61 add %l0, %o0, %l0
63 add %l2, %l0, %i0
/openbmc/linux/arch/sparc/power/
H A Dhibernate_asm.S50 /* Write restore_pblist to %l0 */
51 sethi %hi(restore_pblist), %l0
52 ldx [%l0 + %lo(restore_pblist)], %l0
71 cmp %l0, %g0
73 sub %l0, %g7, %l0
75 ldxa [%l0 ] %asi, %l1 /* address */
76 ldxa [%l0 + 8] %asi, %l2 /* orig_address */
92 ldxa [%l0 + 16] %asi, %l0
/openbmc/bmcweb/static/images/
H A DDMTF_Redfish_logo_2017.svg26 …l0.1,0l9,5.6 l16.4,10.3l10.9,6.8l11.4,7.1l2.3,1.5c0.5,0.3,1.1,0.6,1.6,0.7c2.2,0.8,4.7,0.5,6.8-0.7l…
27 …l0.5-0.2l60.4,7.6c-11.8-3.9-50.3-16.6-63.6-20.9l-0.3-0.1l0-0.6c0-0.2,0-0.3,0-0.5l0.1-0.8c0.1-0.7,0…
49 …-0.4,0.7-1.7,1.1-3.9,1.1c-2.1,0-3.3-0.2-3.8-0.8c-0.5-0.5-0.7-1.8-0.7-3.9l0-2.5l0-2.8c0-2,0.2-3.2,0…
50 …-0.4,0.7-1.7,1.1-3.9,1.1c-2.1,0-3.3-0.2-3.8-0.8c-0.5-0.5-0.7-1.8-0.7-3.9l0-2.5l0-2.8c0-2,0.2-3.2,0…
51 …-0.4,0.7-1.7,1.1-3.9,1.1c-2.1,0-3.3-0.2-3.8-0.8c-0.5-0.5-0.7-1.8-0.7-3.9l0-2.5l0-2.8c0-2,0.2-3.2,0…
52 …9-1.1-3.3-1.7-7.1-1.7c-3.9,0-6.2,0.6-7.1,1.7c-0.6,0.8-1,2.4-1.2,4.8l3.8,2.4l0-1 c0-2,0.2-3.2,0.7-3…
54 …,0.4,0.4,0.6,0.5l3.9-2.5c-0.6-0.1-1-0.3-1.2-0.5c-0.5-0.5-0.7-1.8-0.7-3.9l0-2.5l0-2.8 c0-2,0.2-3.2,…
59 …0-6.2,0.6-7.1,1.7c-0.9,1.1-1.4,4.1-1.4,8.9c0,1.7,0.1,3.2,0.2,4.4l3.8-2.4l0-2.1l0-2.8 c0-2,0.2-3.2,…
64 …-0.4,0.7-1.7,1.1-3.9,1.1c-2.1,0-3.3-0.2-3.8-0.8c-0.5-0.5-0.7-1.8-0.7-3.9l0-2.5l0-2.4l-2.9,1.8l-1-0…
65 …0.4,0.7-1.7,1.1-3.9,1.1c-2.1,0-3.3-0.2-3.8-0.8 c-0.5-0.5-0.7-1.8-0.7-3.9l0-2.5l0-2.8c0-2,0.2-3.2,0…
[all …]
/openbmc/linux/Documentation/virt/kvm/x86/
H A Drunning-nested-guests.rst23 | L0 (Host Hypervisor) |
31 - L0 – level-0; the bare metal host, running KVM
33 - L1 – level-1 guest; a VM running on L0; also called the "guest
44 resulting in at least four levels in a nested setup — L0 (bare
48 This document will stick with the three-level terminology (L0,
88 1. On the bare metal host (L0), list the kernel modules and ensure that
128 metal host (L0). Parameters for Intel hosts::
147 Once your bare metal host (L0) is configured for nesting, you should be
165 1. On the host hypervisor (L0), enable the ``nested`` parameter on
217 L0, L1 and L2; this can result in tedious back-n-forth between the bug
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Datomic64-arcv2.h57 " " #op1 " %L0, %L0, %L2 \n" \
74 " " #op1 " %L0, %L0, %L2 \n" \
96 " " #op1 " %L1, %L0, %L3 \n" \
149 " brne %L0, %L2, 2f \n" in ATOMIC64_OPS()
193 " sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n" in arch_atomic64_dec_if_positive()
217 " brne %L0, %L4, 2f # continue to add since v != u \n" in arch_atomic64_fetch_add_unless()
220 " add.f %L1, %L0, %L3 \n" in arch_atomic64_fetch_add_unless()
/openbmc/linux/arch/alpha/lib/
H A Dev67-strncat.S20 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
58 bsr $23, __stxncpy # L0 :/* Now do the append. */
65 ret # L0 :
81 ret # L0 :
87 ret # L0 :
93 ret # L0 :
H A Dev67-strlen.S19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
48 ret $31, ($26) # L0 :
/openbmc/linux/drivers/cpufreq/
H A Darmada-37xx-cpufreq.c209 * For Armada 37xx soc, L0(VSET0) VDD AVS value is set to SVC revision
211 * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
213 * - L1 voltage should be about 100mv smaller than L0 voltage
214 * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
216 * on L0 voltage and fill all AVS values to the AVS value table.
230 /* Get L0 VDD min value */ in armada37xx_cpufreq_avs_configure()
235 pr_err("L0 VDD MIN %d is not correct.\n", l0_vdd_min); in armada37xx_cpufreq_avs_configure()
242 * If L0 voltage is smaller than 1000mv, then all VDD sets in armada37xx_cpufreq_avs_configure()
243 * use L0 voltage; in armada37xx_cpufreq_avs_configure()
251 * Set the avs values for load L0 and L1 when base CPU frequency in armada37xx_cpufreq_avs_configure()
[all …]
/openbmc/qemu/target/i386/
H A Dmonitor.c141 uint64_t l0, uint64_t pml4_addr) in tlb_info_la48() argument
164 print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30), in tlb_info_la48()
179 print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) + in tlb_info_la48()
191 print_pte(mon, env, (l0 << 48) + (l1 << 39) + in tlb_info_la48()
203 uint64_t l0; in tlb_info_la57() local
208 for (l0 = 0; l0 < 512; l0++) { in tlb_info_la57()
209 cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8); in tlb_info_la57()
212 tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL); in tlb_info_la57()
456 uint64_t l0, l1, l2, l3, l4; in mem_info_la57() local
463 for (l0 = 0; l0 < 512; l0++) { in mem_info_la57()
[all …]
/openbmc/u-boot/drivers/video/tegra124/
H A Ddisplayport.h131 /* postcursor2 L0 */
133 /* pre-emphasis: L0, L1, L2, L3 */
134 {0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */
166 /* postcursor2 L0 */
168 /* pre-emphasis: L0, L1, L2, L3 */
169 {0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */
201 /* postcursor2 L0 */
203 /* pre-emphasis: L0, L1, L2, L3 */
204 {0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */
236 /* postcursor2 L0 */
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-interconnect.json367 "BriefDescription": "Cycles in L0",
371 …L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance wi…
475 …L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with som…
484 …L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with som…
493 …L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with som…
502 …L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with som…
511 …L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with som…
520 …L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with som…
529 …L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with som…
538 …L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with som…
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Dio.h253 "dsll32 %L0, %L0, 0" "\n\t" \
254 "dsrl32 %L0, %L0, 0" "\n\t" \
256 "or %L0, %L0, %M0" "\n\t" \
257 "sd %L0, %2" "\n\t" \
277 "ld %L0, %1" "\n\t" \
278 "dsra32 %M0, %L0, 0" "\n\t" \
279 "sll %L0, %L0, 0" "\n\t" \
/openbmc/linux/arch/mips/include/asm/
H A Dio.h246 "dsll32 %L0, %L0, 0" "\n\t" \
247 "dsrl32 %L0, %L0, 0" "\n\t" \
249 "or %L0, %L0, %M0" "\n\t" \
250 "sd %L0, %2" "\n\t" \
280 "ld %L0, %1" "\n\t" \
281 "dsra32 %M0, %L0, 0" "\n\t" \
282 "sll %L0, %L0, 0" "\n\t" \

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