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/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/openbmc/linux/arch/riscv/kernel/
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include "copy-unaligned.h"
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
37 /* Host ISA bitmap */
40 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
49 * @isa_bitmap: ISA bitmap to use
52 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
63 * __riscv_isa_extension_available() - Check whether given extension
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H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
36 return -ENODEV; in riscv_of_processor_hartid()
44 return -ENODEV; in riscv_of_processor_hartid()
51 const char *isa; in riscv_early_of_processor_hartid() local
55 return -ENODEV; in riscv_early_of_processor_hartid()
61 return -ENODEV; in riscv_early_of_processor_hartid()
66 return -ENODEV; in riscv_early_of_processor_hartid()
69 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
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H A Dsys_riscv.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <asm-generic/mman-common.h>
26 return -EINVAL; in riscv_sys_mmap()
29 offset >> (PAGE_SHIFT - page_shift_offset)); in riscv_sys_mmap()
55 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
60 * thread->hart mappings), so we've defined a RISC-V specific system call to
73 return -EINVAL; in SYSCALL_DEFINE3()
75 flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); in SYSCALL_DEFINE3()
88 u64 id = -1ULL; in hwprobe_arch_id()
95 switch (pair->key) { in hwprobe_arch_id()
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/openbmc/linux/Documentation/riscv/
H A Duabi.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
6 ISA string ordering in /proc/cpuinfo
7 ------------------------------------
9 The canonical order of ISA extension names in the ISA string is defined in
14 #. Single-letter extensions come first, in canonical order.
17 #. All multi-letter extensions will be separated from other extensions by an
20 #. Additional standard extensions (starting with 'Z') will be sorted after
21 single-letter extensions and before any higher-privileged extensions.
23 #. For additional standard extensions, the first letter following the 'Z'
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H A Dhwprobe.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will
24 be only be valid if all CPUs in the given set have the same value. Otherwise -1
25 will be returned. For boolean-like keys, the value returned will be a logical
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/openbmc/openbmc/poky/meta/recipes-devtools/gcc/gcc/
H A D0011-aarch64-Fix-include-paths-when-S-B.patch3 Date: Tue, 31 Jan 2023 22:03:38 -0800
13 …-c -isystem/mnt/b/yoe/master/build/tmp/work/x86_64-linux/gcc-cross-aarch64/13.0.1-r0/recipe-sysr…
15 …from ../../../../../../../work-shared/gcc-13.0.1-r0/gcc-b2ec2504af77b35e748067eeb846821d12a6b6b4/g…
16 ./config/aarch64/aarch64.h:164:10: fatal error: aarch64-option-extensions.def: No such file or dire…
17 164 | #include "aarch64-option-extensions.def"
23 Upstream-Status: Pending
25 Signed-off-by: Khem Raj <raj.khem@gmail.com>
26 ---
27 gcc/config/aarch64/aarch64.h | 14 +++++++-------
28 1 file changed, 7 insertions(+), 7 deletions(-)
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/openbmc/linux/drivers/net/wireless/cisco/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 tristate "Cisco/Aironet 34X/35X/4500/4800 ISA and PCI cards"
24 This is the standard Linux driver to support Cisco/Aironet ISA and
27 - with or without encryption) as well as card before the Cisco
30 This driver support both the standard Linux Wireless Extensions
50 - with or without encryption) as well as card before the Cisco
55 This driver support both the standard Linux Wireless Extensions
/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_onereg.c1 // SPDX-License-Identifier: GPL-2.0
25 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
27 /* Single letter extensions (alphabetically sorted) */
36 /* Multi letter extensions (alphabetically sorted) */
115 set_bit(host_isa, vcpu->arch.isa); in kvm_riscv_vcpu_setup_isa()
123 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_config()
124 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_config()
129 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_config()
130 return -EINVAL; in kvm_riscv_vcpu_get_reg_config()
133 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_get_reg_config()
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/openbmc/qemu/target/riscv/
H A DXVentanaCondOps.decode2 # RISC-V translation routines for the XVentanaCondOps extension
6 # SPDX-License-Identifier: LGPL-2.1-or-later
8 # Reference: VTx-family custom instructions
9 # Custom ISA extensions for Ventana Micro Systems RISC-V cores
10 … (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custo…
23 # *** RV64 Custom-3 Extension ***
/openbmc/linux/arch/riscv/include/asm/
H A Dcpufeature.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright 2022-2023 Rivos, Inc
23 DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
30 /* Per-cpu ISA extensions. */
H A Dhwcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/alternative-macros.h>
16 #define RISCV_ISA_EXT_a ('a' - 'a')
17 #define RISCV_ISA_EXT_b ('b' - 'a')
18 #define RISCV_ISA_EXT_c ('c' - 'a')
19 #define RISCV_ISA_EXT_d ('d' - 'a')
20 #define RISCV_ISA_EXT_f ('f' - 'a')
21 #define RISCV_ISA_EXT_h ('h' - 'a')
22 #define RISCV_ISA_EXT_i ('i' - 'a')
23 #define RISCV_ISA_EXT_j ('j' - 'a')
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H A Delf.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
37 #define elf_check_arch(x) (((x)->e_machine == EM_RISCV) && \
38 ((x)->e_ident[EI_CLASS] == ELF_CLASS))
58 0x7ff >> (PAGE_SHIFT - 12) : \
59 0x3ffff >> (PAGE_SHIFT - 12))
61 #define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12))
66 * Provides information on the availiable set of ISA extensions to userspace,
67 * via a bitmap that coorespends to each single-letter ISA extension. This is
75 (_r)->a1 = _exec_map_addr; \
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/openbmc/qemu/docs/system/
H A Dtarget-i386-desc.rst.inc3 - i440FX host PCI bridge and PIIX3 PCI to ISA bridge
5 - Cirrus CLGD 5446 PCI VGA card or dummy VGA card with Bochs VESA
6 extensions (hardware level, including all non standard modes).
8 - PS/2 mouse and keyboard
10 - 2 PCI IDE interfaces with hard disk and CD-ROM support
12 - Floppy disk
14 - PCI and ISA network adapters
16 - Serial ports
18 - IPMI BMC, either and internal or external one
20 - Creative SoundBlaster 16 sound card
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/openbmc/u-boot/doc/
H A DREADME.NDS321 NDS32 is a new high-performance 32-bit RISC microprocessor core.
5 AndeStar ISA
7 AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
11 - Intermixable 32-bit and 16-bit instruction sets without the need for
13 - 16-bit instructions as a frequently used subset of 32-bit instructions.
14 - RISC-style register-based instruction set.
15 - 32 32-bit General Purpose Registers (GPR).
16 - Upto 1024 User Special Registers (USR) for existing and extension
18 - Rich load/store instructions for...
19 - Single memory access with base address update.
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/openbmc/linux/arch/arm/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 - NEON (Advanced SIMD) extensions
17 tristate "Hash functions: GHASH (PMULL/NEON/ARMv8 Crypto Extensions)"
25 GCM GHASH function (NIST SP800-38D)
28 - PMULL (Polynomial Multiply Long) instructions
29 - NEON (Advanced SIMD) extensions
30 - ARMv8 Crypto Extensions
34 that is part of the ARMv8 Crypto Extensions, or a slower variant that
35 uses the vmull.p8 instruction that is part of the basic NEON ISA.
45 - NEON (Advanced SIMD) extensions
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/openbmc/linux/arch/riscv/
H A DMakefile2 # architecture-specific flags and dependencies.
9 LDFLAGS_vmlinux := -z norelro
11 LDFLAGS_vmlinux += -shared -Bsymbolic -z notext --emit-relocs
12 KBUILD_CFLAGS += -fPIE
15 LDFLAGS_vmlinux += --no-relax
16 KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
18 CC_FLAGS_FTRACE := -fpatchable-function-entry=4
20 CC_FLAGS_FTRACE := -fpatchable-function-entry=2
25 KBUILD_CFLAGS_MODULE += -mcmodel=medany
33 KBUILD_CFLAGS += -mabi=lp64
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
169 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
176 depends on $(cc-option,-fpatchable-function-entry=8)
186 # VA_BITS - PAGE_SHIFT - 3
199 # set if we are running in S-mode and can use SBI calls
206 bool "MMU-based Paged Memory Management Support"
209 Select if you want MMU-based virtualised addressing space
286 This enables function pointer support for non-standard noncoherent
290 def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
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/openbmc/linux/arch/powerpc/platforms/
H A DKconfig.cputype1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
282 default "-mtune=power10" if $(cc-option,-mtune=power10)
283 default "-mtune=power9" if $(cc-option,-mtune=power9)
284 default "-mtune=power8" if $(cc-option,-mtune=power8)
366 This option enables kernel support for larger than 32-bit physical
371 is platform-dependent.
380 This option enables kernel support for the Altivec extensions to the
387 any affect on a non-altivec cpu (it does, however add code to the
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/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
21 #include "exec/exec-all.h"
22 #include "tcg-cpu.h"
30 #include "qemu/error-report.h"
32 #include "hw/core/accel-cpu.h"
33 #include "hw/core/tcg-cpu-ops.h"
39 /* Hash that stores user set extensions */
73 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
76 env->misa_ext |= bit; in riscv_cpu_write_misa_bit()
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/openbmc/linux/arch/x86/events/intel/
H A Dpt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2013-2014, Intel Corporation.
6 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
8 * http://software.intel.com/en-us/intel-isa-extensions
15 * Single-entry ToPA: when this close to region boundary, switch
54 * struct pt_buffer - buffer configuration; one buffer per task_struct or
95 * struct pt_filter - IP range filter configuration
98 * @config: 4-bit field in RTIT_CTL
107 * struct pt_filters - IP range filtering context
117 * struct pt - per-cpu pt context
/openbmc/linux/arch/mips/include/asm/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 +----------------+----------------+----------------+----------------+
20 +----------------+----------------+----------------+----------------+
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
92 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
95 #define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
96 #define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
97 #define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
189 #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
190 #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
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/openbmc/u-boot/include/
H A Dns87308.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
25 unsigned char puc1; /* 3 pull-up control port 1 */
29 unsigned char puc2; /* 7 pull-up control port 2 */
40 #define PWM_WDTO 5 /* 5 watchdog time-out */
53 #define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
56 #define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
198 /* The following sections are for 87308 extensions to the standard compoents it emulates */
200 /* extensions to 16550*/
/openbmc/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
99 bool "ARCompact ISA"
102 The original ARC ISA of ARC600/700 cores
105 bool "ARC ISA v2"
108 ISA for the Next Generation ARC-HS cores
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
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