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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
33 -------------------
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
41 Any RID r in the interval [rid-base, rid-base + length) is associated with
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H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
22 the standard "reset-gpios" and "max-link-speed" properties appear on
34 - enum:
35 - apple,t8103-pcie
36 - apple,t8112-pcie
37 - apple,t6000-pcie
38 - const: apple,pcie
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H A Drcar-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Host
11 - Marek Vasut <marek.vasut+renesas@gmail.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - $ref: pci-bus.yaml#
20 - const: renesas,pcie-r8a7779 # R-Car H1
21 - items:
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/openbmc/linux/arch/sparc/kernel/
H A Dpci_sun4v.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/dma-map-ops.h>
21 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
58 unsigned long prot; /* IOMMU page protections */
72 p->dev = dev; in iommu_batch_start()
73 p->prot = prot; in iommu_batch_start()
74 p->entry = entry; in iommu_batch_start()
75 p->npages = 0; in iommu_batch_start()
78 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
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H A Diommu-common.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
11 #include <linux/dma-mapping.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
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/openbmc/linux/drivers/of/
H A Ddevice.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-direct.h> /* for bus_dma_region */
9 #include <linux/dma-map-ops.h>
19 * of_match_device - Tell if a struct device matches an of_device_id list
29 if (!matches || !dev->of_node || dev->of_node_reused) in of_match_device()
31 return of_match_node(matches, dev->of_node); in of_match_device()
38 struct device_node *node, *of_node = dev->of_node; in of_dma_set_restricted_buffer()
44 count = of_property_count_elems_of_size(of_node, "memory-region", in of_dma_set_restricted_buffer()
47 * If dev->of_node doesn't exist or doesn't contain memory-region, try in of_dma_set_restricted_buffer()
53 of_node, "memory-region", sizeof(u32)); in of_dma_set_restricted_buffer()
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/openbmc/linux/arch/arm64/boot/dts/apple/
H A Dt600x-die0.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
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/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
22 the set of possible ICIDs under a root DPRC and how they map to
23 an IOMMU.
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
28 For arm-smmu binding, see:
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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/openbmc/u-boot/drivers/pci/
H A Dpcie_layerscape_fixup.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
27 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) in ls_pcie_next_lut_index()
28 return pcie->next_lut_index++; in ls_pcie_next_lut_index()
30 return -ENOSPC; /* LUT is full */ in ls_pcie_next_lut_index()
33 /* returns the next available streamid for pcie, -errno if failed */
39 return -EINVAL; in ls_pcie_next_streamid()
47 if (pcie->big_endian) in lut_writel()
48 out_be32(pcie->lut + offset, value); in lut_writel()
50 out_le32(pcie->lut + offset, value); in lut_writel()
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/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-crb-A.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-A";
14 num-lanes = <4>;
15 num-viewport = <8>;
21 iommu-map =
25 iommu-map-mask = <0x031f>;
30 usb-phy = <&cp0_usb3_0_phy0>;
31 phy-names = "usb";
36 usb-phy = <&cp0_usb3_0_phy1>;
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H A Darmada-7040.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-ap806-quad.dtsi"
10 #include "armada-70x0.dtsi"
14 compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
15 "marvell,armada-ap806";
19 iommu-map =
23 iommu-map-mask = <0x031f>;
H A Dcn9130-crb-B.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-B";
14 num-lanes = <1>;
15 num-viewport = <8>;
18 iommu-map =
22 iommu-map-mask = <0x031f>;
27 sata-port@0 {
36 usb-phy = <&cp0_usb3_0_phy0>;
37 phy-names = "usb";
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H A Darmada-8040.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-ap806-quad.dtsi"
10 #include "armada-80x0.dtsi"
14 compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
15 "marvell,armada-ap806";
19 iommu-map =
23 iommu-map-mask = <0x031f>;
/openbmc/linux/drivers/vfio/
H A Dvfio_iommu_type1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
14 * VT-d, but that makes it harder to re-use as theoretically anyone
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userspace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
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/openbmc/linux/arch/sparc/include/asm/
H A Diommu-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 unsigned long *map; member
35 extern void iommu_tbl_pool_init(struct iommu_map_table *iommu,
43 struct iommu_map_table *iommu,
46 unsigned long mask,
49 extern void iommu_tbl_range_free(struct iommu_map_table *iommu,
/openbmc/qemu/hw/i386/
H A Dintel_iommu.c2 * QEMU emulation of an Intel IOMMU (VT-d)
23 #include "qemu/error-report.h"
24 #include "qemu/main-loop.h"
30 #include "hw/qdev-properties.h"
32 #include "hw/i386/apic-msidef.h"
33 #include "hw/i386/x86-iommu.h"
34 #include "hw/pci-host/q35.h"
45 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK)
47 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)
50 #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
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/openbmc/linux/arch/powerpc/include/asm/
H A Diommu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #include <linux/dma-map-ops.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/asm-const.h>
24 #define IOMMU_PAGE_MASK_4K (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
27 #define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
28 #define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
31 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
32 #define DMA64_PROPNAME "linux,dma64-ddr-window-info"
41 * uaddr is a linear map address.
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/openbmc/linux/drivers/iommu/intel/
H A Ddmar.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2008 Intel Corporation
14 * These routines are used by both DMA-remapping and Interrupt-remapping
28 #include <linux/iommu.h>
33 #include "iommu.h"
49 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
51 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
67 static void free_iommu(struct intel_iommu *iommu);
75 if (drhd->include_all) in dmar_register_drhd_unit()
76 list_add_tail_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
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/openbmc/linux/arch/arm/mm/
H A Ddma-mapping.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/dma-mapping.c
5 * Copyright (C) 2000-2004 Russell King
17 #include <linux/dma-direct.h>
18 #include <linux/dma-map-ops.h>
22 #include <linux/iommu.h>
33 #include <asm/dma-iommu.h>
34 #include <asm/mach/map.h>
36 #include <asm/xen/xen-ops.h>
84 if (buf->virt == virt) { in arm_dma_buffer_find()
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/openbmc/qemu/include/hw/i386/
H A Dintel_iommu.h2 * QEMU emulation of an Intel IOMMU (VT-d)
25 #include "hw/i386/x86-iommu.h"
26 #include "qemu/iova-tree.h"
29 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
32 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
34 /* DMAR Hardware Unit Definition address (IOMMU unit) */
49 #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
66 /* Context-Entry */
102 IOMMUMemoryRegion iommu; member
115 * The tree is not needed if no MAP notifier is registered with current
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