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/openbmc/linux/arch/powerpc/boot/dts/
H A Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
H A Dbluestone.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
12 #address-cells = <2>;
13 #size-cells = <1>;
16 dcr-parent = <&{/cpus/cpu@0}>;
25 #address-cells = <1>;
26 #size-cells = <0>;
32 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */
34 i-cache-line-size = <32>;
[all …]
H A Dwarp.dts4 * Copyright (c) 2008-2009 PIKA Technologies
12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <0>; /* Filled in by zImage */
35 timebase-frequency = <0>; /* Filled in by zImage */
36 i-cache-line-size = <32>;
[all …]
H A Dhotfoot.dts4 * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by zImage */
36 timebase-frequency = <0>; /* Filled in by zImage */
37 i-cache-line-size = <0x20>;
[all …]
H A Dobs600.dts8 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
[all …]
H A Dsequoia.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dyosemite.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <0>; /* Filled in by zImage */
39 timebase-frequency = <0>; /* Filled in by zImage */
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
[all …]
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dsocrates.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dkilauea.dts4 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
H A Drainier.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dtqm8560.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
[all …]
H A Dredwood.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
26 #address-cells = <1>;
27 #size-cells = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <32>;
36 d-cache-line-size = <32>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1023rdb.dts4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
37 /include/ "p1023si-pre.dtsi"
42 #address-cells = <2>;
43 #size-cells = <2>;
44 interrupt-parent = <&mpic>;
50 reserved-memory {
51 #address-cells = <2>;
52 #size-cells = <2>;
55 bman_fbpr: bman-fbpr {
59 qman_fqd: qman-fqd {
[all …]
H A Dmpc8572ds.dtsi2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
46 label = "ramdisk-nor";
49 partition@3000000 {
51 label = "diagnostic-nor";
[all …]
H A Dmpc8544ds.dtsi2 * MPC8544DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
46 label = "dtb-nor";
49 partition@20000 {
51 label = "diagnostic-nor";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-cse-qspi.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015 - 2017 Xilinx, Inc.
7 /dts-v1/;
10 #address-cells = <1>;
11 #size-cells = <1>;
13 compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
26 stdout-path = "serial0:115200n8";
32 u-boot,dm-pre-reloc;
36 u-boot,dm-pre-reloc;
37 compatible = "simple-bus";
[all …]
H A Ddra72-evm-common.dtsi2 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
22 stdout-path = &uart1;
25 evm_12v0: fixedregulator-evm12v0 {
27 compatible = "regulator-fixed";
28 regulator-name = "evm_12v0";
29 regulator-min-microvolt = <12000000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra72-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-ipu-dsp-common.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clock/ti-dra7-atl.h>
13 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
20 stdout-path = &uart1;
23 evm_12v0: fixedregulator-evm12v0 {
25 compatible = "regulator-fixed";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
20 - enum:
21 - ti,am64-nand
22 - ti,omap2-nand
29 - description: Interrupt for fifoevent
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-l-50.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Check Point L-50 Board Description
7 /dts-v1/;
10 #include "kirkwood-6281.dtsi"
13 model = "Check Point L-50";
14 compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
23 stdout-path = &uart0;
27 pinctrl: pin-controller@10000 {
28 pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
29 pinctrl-names = "default";
[all …]
/openbmc/qemu/pc-bios/
H A Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]

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