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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmstar,mst-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
21 const: mstar,mst-intc
23 interrupt-controller: true
25 "#interrupt-cells":
33 mstar,irqs-map-range:
37 $ref: /schemas/types.yaml#/definitions/uint32-matrix
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/openbmc/linux/arch/powerpc/sysdev/xics/
H A Dicp-opal.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 * We take the ipi irq but and never return so we need to EOI the IPI, in icp_opal_flush_ipi()
82 /* We might learn about it later, so EOI it */ in icp_opal_get_irq()
94 * of allowing no interrupts allow all. That's still not right, but in icp_opal_set_cpu_priority()
115 * EOI tells us whether there are more interrupts to fetch. in icp_opal_eoi()
145 * Called when an interrupt is received on an off-line CPU to
169 /* EOI the interrupt */ in icp_opal_flush_interrupt()
177 .eoi = icp_opal_eoi,
191 np = of_find_compatible_node(NULL, NULL, "ibm,opal-intc"); in icp_opal_init()
193 return -ENODEV; in icp_opal_init()
/openbmc/qemu/hw/intc/
H A Dioapic.c4 * Copyright (c) 2004-2005 Fabrice Bellard
28 #include "hw/intc/i8259.h"
29 #include "hw/intc/ioapic.h"
30 #include "hw/intc/ioapic_internal.h"
32 #include "hw/qdev-properties.h"
35 #include "hw/i386/apic-msidef.h"
36 #include "hw/i386/x86-iommu.h"
65 info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; in ioapic_entry_parse()
66 info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; in ioapic_entry_parse()
73 info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff; in ioapic_entry_parse()
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H A Dspapr_xive.c4 * Copyright (c) 2017-2018, IBM Corporation.
7 * COPYING file in the top-level directory.
14 #include "qemu/error-report.h"
25 #include "hw/qdev-properties.h"
52 return nvt_idx - SPAPR_XIVE_NVT_BASE; in spapr_xive_nvt_to_target()
65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; in spapr_xive_cpu_to_nvt()
75 return -1; in spapr_xive_target_to_nvt()
112 *out_end_idx = (cpu->vcpu_id << 3) + prio; in spapr_xive_cpu_to_end()
122 return -1; in spapr_xive_target_to_end()
137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); in spapr_xive_end_pic_print_info()
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H A Dspapr_xive_kvm.c4 * Copyright (c) 2017-2019, IBM Corporation.
7 * COPYING file in the top-level directory.
12 #include "qemu/error-report.h"
46 if (enabled_cpu->vcpu_id == vcpu_id) { in kvm_cpu_is_enabled()
59 enabled_cpu->vcpu_id = vcpu_id; in kvm_cpu_enable()
79 SpaprXive *xive = SPAPR_XIVE(tctx->xptr); in kvmppc_xive_cpu_set_state()
83 assert(xive->fd != -1); in kvmppc_xive_cpu_set_state()
86 state[0] = *((uint64_t *) &tctx->regs[TM_QW1_OS]); in kvmppc_xive_cpu_set_state()
88 ret = kvm_set_one_reg(tctx->cs, KVM_REG_PPC_VP_STATE, state); in kvmppc_xive_cpu_set_state()
90 error_setg_errno(errp, -ret, in kvmppc_xive_cpu_set_state()
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H A Dpnv_xive.c4 * Copyright (c) 2017-2019, IBM Corporation.
7 * COPYING file in the top-level directory.
25 #include "hw/qdev-properties.h"
55 * 0 - IPI,
56 * 1 - HWD,
57 * 2 - First escalate,
58 * 3 - Second escalate,
59 * 4 - Redistribution,
60 * 5 - IPI cascaded queue ?
66 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \
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H A Dxics.c20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
33 #include "hw/qdev-properties.h"
34 #include "qemu/error-report.h"
38 #include "hw/intc/intc.h"
55 cpu_index = icp->cs ? icp->cs->cpu_index : -1; in icp_pic_print_info()
57 if (!icp->output) { in icp_pic_print_info()
66 cpu_index, icp->xirr, icp->xirr_owner, in icp_pic_print_info()
67 icp->pending_priority, icp->mfrr); in icp_pic_print_info()
75 ics->offset, ics->offset + ics->nr_irqs - 1, ics); in ics_pic_print_info()
77 if (!ics->irqs) { in ics_pic_print_info()
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H A Dapic.c4 * Copyright (c) 2004-2005 Fabrice Bellard
21 #include "qemu/error-report.h"
24 #include "hw/intc/ioapic.h"
25 #include "hw/intc/i8259.h"
26 #include "hw/intc/kvm_irqcount.h"
28 #include "qemu/host-utils.h"
31 #include "hw/i386/apic-msidef.h"
58 max_apics = (max_apic_id + word_size - 1) & ~(word_size - 1); in apic_set_max_apic_id()
68 return 31 - clz32(value); in apic_fls_bit()
85 /* return -1 if no bit is set */
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H A Dgicv3_internal.h2 * ARM GICv3 support - internal interfaces
28 #include "hw/intc/arm_gicv3_common.h"
244 /* Note that EOI shares with the top bit of the pINTID field */
376 #define ICID_MASK ((1U << ICID_LENGTH) - 1)
380 #define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LENGTH) - 1)
389 #define EVENTID_MASK ((1ULL << 32) - 1)
462 * the value of that field in memory cannot be relied upon -- older
541 if (s->cpu[0].gicr_typer & GICR_TYPER_VLPIS) { in gicv3_redist_size()
617 * @doorbell: doorbell (physical) interrupt number (1023 for "no doorbell")
638 * the cpuif and does not need to do the not-running-on-this-vcpu checks.)
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/openbmc/linux/drivers/irqchip/
H A Dirq-mst-intc.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
4 * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
49 raw_spin_lock_irqsave(&cd->lock, flags); in mst_set_irq()
50 val = readw_relaxed(cd->base + offset) | mask; in mst_set_irq()
51 writew_relaxed(val, cd->base + offset); in mst_set_irq()
52 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_set_irq()
65 raw_spin_lock_irqsave(&cd->lock, flags); in mst_clear_irq()
66 val = readw_relaxed(cd->base + offset) & ~mask; in mst_clear_irq()
67 writew_relaxed(val, cd->base + offset); in mst_clear_irq()
68 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_clear_irq()
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/openbmc/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
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/openbmc/qemu/hw/i386/
H A Dpc.c4 * Copyright (c) 2003-2004 Fabrice Bellard
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 #include "hw/char/serial-isa.h"
30 #include "hw/hyperv/hv-balloon.h"
34 #include "hw/ide/ide-bus.h"
38 #include "hw/intc/i8259.h"
48 #include "qemu/error-report.h"
50 #include "acpi-build.h"
55 #include "hw/net/ne2000-isa.h"
56 #include "hw/virtio/virtio-iommu.h"
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/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_hv.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Kevin Wolf <mail@kevin-wolf.de>
32 #include <linux/page-flags.h>
50 #include <asm/ppc-opcode.h>
51 #include <asm/asm-prototypes.h>
73 #include <asm/pnv-pci.h>
108 MODULE_PARM_DESC(dynamic_mt_modes, "Set of allowed dynamic micro-threading modes: 0 (= none), 2, 4,…
170 vcpu = READ_ONCE(vc->runnable_threads[i]); in next_runnable_thread()
181 for (i = -1; (vcpu = next_runnable_thread(vc, &i)); )
215 if (paca_ptrs[cpu]->kvm_hstate.xics_phys) { in kvmppc_ipi_thread()
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