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/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_5445x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
89 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
91 u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
92 u16 cir; /* Chip Identification Register (Read-only) */
96 u16 uocsr; /* USB On-the-Go Controller Status Register */
101 u8 podr_fec0h; /* FEC0 High Port Output Data Register */
102 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
103 u8 podr_ssi; /* SSI Port Output Data Register */
[all …]
/openbmc/u-boot/board/nvidia/p2371-0000/
H A Dpinmux-config-p2371-0000.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
9 * To generate this file, use the tegra-pinmux-scripts tool available from
10 * https://github.com/NVIDIA/tegra-pinmux-scripts
11 * Run "board-to-uboot.py p2371-0000".
89 PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
90 PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
91 PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
92 PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
93 PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
[all …]
/openbmc/u-boot/board/nvidia/p2371-2180/
H A Dpinmux-config-p2371-2180.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
9 * To generate this file, use the tegra-pinmux-scripts tool available from
10 * https://github.com/NVIDIA/tegra-pinmux-scripts
11 * Run "board-to-uboot.py p2371-2180".
100 PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
101 PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
102 PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
103 PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
104 PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
[all …]
/openbmc/witherspoon-pfault-analysis/
H A Dgpio.hpp22 * If the GPIO is an input or output
27 output enumerator
31 * The possible values - low or high
36 high enumerator
59 * @param[in] device - the GPIO device file
60 * @param[in] gpio - the GPIO number
61 * @param[in] direction - the GPIO direction
72 * @return Value - the GPIO value
77 * Sets the GPIO value to low or high
81 * @param[in] Value - the value to set
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/openbmc/phosphor-power/
H A Dgpio.hpp22 * If the GPIO is an input or output
27 output enumerator
31 * The possible values - low or high
36 high enumerator
59 * @param[in] device - the GPIO device file
60 * @param[in] gpio - the GPIO number
61 * @param[in] direction - the GPIO direction
72 * @return Value - the GPIO value
77 * Sets the GPIO value to low or high
81 * @param[in] Value - the value to set
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/openbmc/qemu/include/hw/gpio/
H A Dnrf51_gpio.h2 * nRF51 System-on-Chip general purpose input/output register definition
6 * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin.
7 * Level -1: Externally Disconnected/Floating; Pull-up/down will be regarded
9 * Level 1: Input externally driven HIGH
10 * + Unnamed GPIO outputs 0-31:
11 * Level -1: Disconnected/Floating
13 * Level 1: Driven HIGH
16 * + The nRF51 GPIO output driver supports two modes, standard and high-current
20 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
23 * the COPYING file in the top-level directory.
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/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dst,stm32-pinctrl.txt4 controller. It controls the input/output settings on the available pins and
5 also provides ability to multiplex and configure the output of various on-chip
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
15 - ranges : defines mapping between pin controller node (parent) to
16 gpio-bank node (children).
17 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
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H A Dpinctrl-bindings.txt4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
15 need to reconfigure pins at run-time, for example to tri-state pins when the
47 pinctrl-0: List of phandles, each pointing at a pin configuration
65 pinctrl-1: List of phandles, each pointing at a pin configuration
68 pinctrl-n: List of phandles, each pointing at a pin configuration
70 pinctrl-names: The list of names to assign states. List entry 0 defines the
78 pinctrl-names = "active", "idle";
79 pinctrl-0 = <&state_0_node_a>;
80 pinctrl-1 = <&state_1_node_a &state_1_node_b>;
85 pinctrl-0 = <&state_0_node_a>;
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/openbmc/u-boot/arch/arm/dts/
H A Dast2600-greatlakes.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
9 compatible = "facebook,greatlakes-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
27 clock-frequency = <800000000>;
30 clock-frequency = <800000000>;
36 u-boot,dm-pre-reloc;
41 clock-frequency = <400000000>;
58 pinctrl-names = "default";
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H A Dkirkwood-openrd.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 #include "kirkwood-6281.dtsi"
22 stdout-path = &uart0;
26 pinctrl: pin-controller@10000 {
27 pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>;
28 pinctrl-names = "default";
30 pmx_select28: pmx-select-rs232-rs485 {
34 pmx_sdio_cd: pmx-sdio-cd {
38 pmx_select34: pmx-select-uart-sd {
49 nr-ports = <2>;
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/openbmc/openbmc/meta-ampere/meta-jade/recipes-ampere/platform/ampere-platform-init/
H A Dampere_platform_init.sh4 # shellcheck source=meta-ampere/meta-jade/recipes-ampere/platform/ampere-platform-init/mtjade_platf…
8 pre-platform-init
14 echo "CONFIGURE: gpio pins to output high after AC power"
18 echo "CONFIGURE: gpio pins to output low after AC power"
30 echo "CONFIGURE: gpio pins to output high"
34 echo "CONFIGURE: gpio pins to output low"
44 post-platform-init
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dgpio-pcf857x.txt1 * PCF857x-compatible I/O expanders
3 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
4 driven high by a pull-up current source or driven low to ground. This combines
5 the direction and output level into a single bit per line, which can't be read
7 (a) as output and driving the signal low/high, or (b) as input and reporting a
8 low/high value, without knowing the last value written since the chip came out
14 - compatible: should be one of the following.
15 - "maxim,max7328": For the Maxim MAX7378
16 - "maxim,max7329": For the Maxim MAX7329
17 - "nxp,pca8574": For the NXP PCA8574
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/openbmc/openbmc/meta-quanta/meta-q71l/recipes-phosphor/quanta-powerctrl/files/
H A Dinit_once.sh3 # Set all output GPIOs as such and drive them with reasonable values.
5 if [ $# -ne 2 ]; then
18 set_gpio_active_low $((GPIO_BASE + 128 + 4)) high
21 set_gpio_active_low $((GPIO_BASE + 128 + 6)) high
24 set_gpio_active_low $((GPIO_BASE + 0 + 3)) high
27 set_gpio_active_low $((GPIO_BASE + 32 + 4)) high
30 set_gpio_active_low $((GPIO_BASE + 24 + 3)) high
/openbmc/u-boot/board/nvidia/p2571/
H A Dpinmux-config-p2571.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
9 * To generate this file, use the tegra-pinmux-scripts tool available from
10 * https://github.com/NVIDIA/tegra-pinmux-scripts
11 * Run "board-to-uboot.py p2571".
65 PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
66 PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
67 PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
68 PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
70 PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
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/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
84 #define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))
121 return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE; in get_gpio_id()
137 r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': " in disconnect_all_pins()
138 "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }", in disconnect_all_pins()
151 r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':" in get_disconnected_pins()
152 " { 'path': %s, 'property': 'disconnected-pins'} }", path); in get_disconnected_pins()
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/openbmc/u-boot/tools/patman/
H A Dtout.py1 # SPDX-License-Identifier: GPL-2.0+
4 # Terminal output logging.
11 # Output verbosity levels that we support
21 This class handles output of progress and other useful information
23 output nothing but errors at verbosity zero.
25 The idea is that modules set up an Output object early in their years and pass
26 it around to other modules that need it. This keeps the output under control
78 """Output a message to the terminal.
82 this as high as the currently selected level.
93 """Output a message to the terminal.
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/openbmc/u-boot/arch/sandbox/include/asm/
H A Dgpio.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * wants to change the GPIO values reported to U-Boot.
13 * We use the generic interface, and add a back-channel.
15 * The back-channel functions are declared in this file. They should not be used
19 * a simulated GPIO. From then on, normal code in U-Boot will see this new
24 #include <asm-generic/gpio.h>
31 * @return -1 on error, 0 if GPIO is low, >0 if high
40 * @param value value to set (0 for low, non-zero for high)
41 * @return -1 on error, 0 if ok
50 * @param value value to set (0 for enabled open drain mode, non-zero for
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/openbmc/openbmc/meta-ampere/meta-mitchell/recipes-ampere/platform/ampere-platform-init/
H A Dampere_platform_init.sh4 # shellcheck source=meta-ampere/meta-mitchell/recipes-ampere/platform/ampere-platform-init/mtmitche…
5 # shellcheck source=meta-ampere/meta-common/recipes-ampere/platform/ampere-utils/utils-lib.sh
7 source /usr/sbin/utils-lib.sh
9 function socket-based-fan-conf-update() {
10 echo "Checking phosphor-fan configurations based on CPU 1 presence..."
11 …fanControlConfDir="/usr/share/phosphor-fan-presence/control/com.ampere.Hardware.Chassis.Model.MtMi…
24 if [ -f "$fanControlConfDir/$refConf" ]; then
36 board_id=$(i2cget -y -a 0 0x20 0x0 b)
57 # P0[7] -> GPI[1] and P0[6] -> GPI[0]
60 if [[ $md_id_7_6_5_4 -gt 8 ]]; then
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/openbmc/u-boot/drivers/video/rockchip/
H A DKconfig8 # Author: Eric Gao <eric.gao@rock-chips.com>
15 Rockchip SoCs provide video output capabilities for High-Definition
16 Multimedia Interface (HDMI), Low-voltage Differential Signalling
19 This driver supports the on-chip video output device, and targets the
29 framebuffer during device-model binding/probing.
38 framebuffer during device-model binding/probing.
52 This enables Low-voltage Differential Signaling(LVDS) display
60 This enables High-Definition Multimedia Interface display support.
/openbmc/u-boot/include/dm/
H A Dpinctrl.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 * struct pinconf_param - pin config parameters
27 * struct pinctrl_ops - pin control operations, to be implemented by
47 * in this driver. (necessary for pin-muxing)
50 * certain device to. (necessary for pin-muxing)
54 * may be ignored. (necessary for pin-muxing against a single pin)
59 * (necessary for pin-muxing against a pin group)
60 * @pinconf_num_params: number of driver-specific parameters to be parsed
61 * from device trees (necessary for pin-configuration)
63 * device trees (necessary for pin-configuration)
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpinmux.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2014
76 /* Defines a pin group cfg's low-power mode select */
82 PMUX_LPMD_NONE = -1,
91 PMUX_SCHMT_NONE = -1,
96 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
100 PMUX_HSM_NONE = -1,
116 u32 io:2; /* input or output PMUX_PIN_... */
122 u32 od:2; /* open-drain or push-pull driver */
125 u32 ioreset:2; /* input/output reset PMUX_PIN... */
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/openbmc/qemu/python/qemu/qmp/
H A Dutil.py19 # --------------------------
21 # --------------------------
24 def get_or_create_event_loop() -> asyncio.AbstractEventLoop:
31 generally not be used in any asyncio-native applications.
50 async def flush(writer: asyncio.StreamWriter) -> None:
55 the "high-water mark". This function ensures we flush the entire
56 buffer -- by setting the high water mark to 0 and then calling
60 transport = cast( # type: ignore[redundant-cast]
65 low, high = transport.get_write_buffer_limits() # type: ignore
70 transport.set_write_buffer_limits(high, low)
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/openbmc/u-boot/drivers/gpio/
H A Dtegra_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2010-2012,2015
22 #include <dm/device-internal.h>
23 #include <dt-bindings/gpio/gpio.h>
33 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
36 /* Information about each port at run-time */
39 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
46 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in get_config()
50 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); in get_config()
63 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in set_config()
[all …]
H A Dkw_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * arch/arm/plat-orion/gpio.c
9 * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
12 * Dieter Kiermaier dk-arm-linux@gmx.de
38 static void __set_level(unsigned pin, int high) in __set_level() argument
43 if (high) in __set_level()
115 /* Configure GPIO output value. */ in kw_gpio_direction_output()
138 /* Configure GPIO output value. */ in kw_gpio_set_value()
144 /* Set output value to zero. */ in kw_gpio_set_blink()
/openbmc/u-boot/board/freescale/ls1012aqds/
H A DREADME2 --------
3 QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
6 optimized to support the high-bandwidth DDR3L memory and
7 a full complement of high-speed SerDes ports.
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
15 -----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
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