| /openbmc/sdbusplus/docs/yaml/ |
| H A D | interface.md | 9 An interface YAML may have the following sections:
29 A common problem we have found with D-Bus interfaces is having a consistent way
31 meaning to integers, as a C compiler might do, or to have specific strings
40 What we have done in `sdbus++` is to consider enumerations as a first-class
42 have a C++ enumeration defined for it. At a D-Bus level any property or method
50 An enumeration must have the YAML properties `name` and `values` and may
142 A method must have the YAML property `name` and may optionally have
144 must have a `name`, `type`, and optional `description`. Each return must have a
145 `type` and may optionally have a `name` and `description`. Flags are a list of
182 A property must have the YAML property `name` and `type` and may optionally have
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| /openbmc/openbmc/poky/meta/recipes-connectivity/ppp/ppp/ |
| H A D | 0001-pppd-pppdconf.h-remove-erroneous-generated-header.patch | 56 -/* Have Microsoft CHAP support */
59 -/* Have Microsoft LAN Manager support */
62 -/* Have Microsoft MPPE support */
65 -/* Have multilink support */
68 -/* Have packet activity filter support */
71 -/* Have support for loadable plugins */
74 -/* Have Callback Protocol support */
80 -/* Have IPv6 Control Protocol */
86 -/* Have EAP-SRP authentication support */
89 -/* Have EAP-TLS authentication support */
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| /openbmc/phosphor-power/phosphor-regulators/test/ |
| H A D | config_file_parser_tests.cpp | 145 ADD_FAILURE() << "Should not have reached this line."; in TEST()
170 ADD_FAILURE() << "Should not have reached this line."; in TEST()
187 ADD_FAILURE() << "Should not have reached this line."; in TEST()
204 ADD_FAILURE() << "Should not have reached this line."; in TEST()
226 ADD_FAILURE() << "Should not have reached this line."; in TEST()
518 ADD_FAILURE() << "Should not have reached this line."; in TEST()
534 ADD_FAILURE() << "Should not have reached this line."; in TEST()
551 ADD_FAILURE() << "Should not have reached this line."; in TEST()
570 ADD_FAILURE() << "Should not have reached this line."; in TEST()
602 ADD_FAILURE() << "Should not have reached this line."; in TEST()
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| H A D | id_map_tests.cpp | 62 ADD_FAILURE() << "Should not have caught exception."; in TEST()
78 ADD_FAILURE() << "Should not have reached this line."; in TEST()
110 ADD_FAILURE() << "Should not have caught exception."; in TEST()
121 ADD_FAILURE() << "Should not have reached this line."; in TEST()
152 ADD_FAILURE() << "Should not have caught exception."; in TEST()
164 ADD_FAILURE() << "Should not have reached this line."; in TEST()
198 ADD_FAILURE() << "Should not have caught exception."; in TEST()
205 ADD_FAILURE() << "Should not have reached this line."; in TEST()
214 ADD_FAILURE() << "Should not have caught exception."; in TEST()
236 ADD_FAILURE() << "Should not have caught exception."; in TEST()
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| /openbmc/u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | README | 13 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
14 has 64-bit DDR. All others have 32-bit DDR.
30 they don't have regular DIMMs.
40 Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
43 in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/android-tools/android-tools/build/ |
| H A D | 0001-Riscv-Add-risc-v-Android-config-header.patch | 63 + * Do we have pthread_setname_np()?
71 + * Do we have the futex syscall?
109 + * Define this if you have <termio.h>
114 + * Define this if you have <sys/sendfile.h>
124 + * Define this if you have sys/uio.h
135 + * Define this if we have localtime_r().
140 + * Define this if we have gethostbyname_r().
145 + * Define this if we have ioctl().
155 + * Define this if have clock_gettime() and friends
160 + * Define this if we have linux style epoll()
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| /openbmc/u-boot/doc/ |
| H A D | README.generic-board | 15 All boards and architectures have moved to this as of mid 2016.
25 Related to this, the global_data and bd_t structures now have a core set of
27 have been moved to separate structures.
90 few issues to be solved. So I have chosen both ARM and x86 for this series.
91 After a suggestion from Wolfgang I have added PPC also. This is the
92 largest and most feature-full board, so hopefully we have all bases
97 architectures include and need it, most global_data.h files already have
101 for now I have judged that to be counter-productive.
104 be accessing it. I have done this in the same way as global_data and the
117 I have run-tested ARM on Tegra Seaboard only. To try it out, define
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| /openbmc/docs/designs/mctp/ |
| H A D | mctp.md | 7 Currently, we have a few different methods of communication between host and
10 started to hit some of the limitations of IPMI (for example, we have need
15 platforms provide. Then, on top of MCTP, we have the opportunity to move to
23 these; we currently have BT and KCS (both defined as part of the IPMI 2.0
26 Some efforts of improving the hardware transport mechanism of IPMI have been
68 - Have a simple serialisation and deserialisation format, to enable
69 implementations in host firmware, which have widely varying runtime
72 - Allow different hardware channels, as we have a wide variety of target
75 - Be usable over simple hardware implementations, but have a facility for higher
99 There have been two main alternatives to an MCTP implementation in OpenBMC:
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| /openbmc/phosphor-power/phosphor-regulators/test/actions/ |
| H A D | i2c_write_bit_action_tests.cpp | 54 ADD_FAILURE() << "Should not have caught exception."; in TEST()
61 ADD_FAILURE() << "Should not have reached this line."; in TEST()
69 ADD_FAILURE() << "Should not have caught exception."; in TEST()
76 ADD_FAILURE() << "Should not have reached this line."; in TEST()
84 ADD_FAILURE() << "Should not have caught exception."; in TEST()
122 ADD_FAILURE() << "Should not have caught exception."; in TEST()
157 ADD_FAILURE() << "Should not have caught exception."; in TEST()
170 ADD_FAILURE() << "Should not have reached this line."; in TEST()
178 ADD_FAILURE() << "Should not have caught exception."; in TEST()
206 ADD_FAILURE() << "Should not have reached this line."; in TEST()
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| H A D | i2c_compare_bit_action_tests.cpp | 53 ADD_FAILURE() << "Should not have caught exception."; in TEST()
60 ADD_FAILURE() << "Should not have reached this line."; in TEST()
68 ADD_FAILURE() << "Should not have caught exception."; in TEST()
75 ADD_FAILURE() << "Should not have reached this line."; in TEST()
83 ADD_FAILURE() << "Should not have caught exception."; in TEST()
147 ADD_FAILURE() << "Should not have caught exception."; in TEST()
160 ADD_FAILURE() << "Should not have reached this line."; in TEST()
168 ADD_FAILURE() << "Should not have caught exception."; in TEST()
195 ADD_FAILURE() << "Should not have reached this line."; in TEST()
205 ADD_FAILURE() << "Should not have reached this line."; in TEST()
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| H A D | pmbus_write_vout_command_action_tests.cpp | 65 ADD_FAILURE() << "Should not have caught exception."; in TEST()
83 ADD_FAILURE() << "Should not have caught exception."; in TEST()
94 ADD_FAILURE() << "Should not have reached this line."; in TEST()
102 ADD_FAILURE() << "Should not have caught exception."; in TEST()
148 ADD_FAILURE() << "Should not have caught exception."; in TEST()
193 ADD_FAILURE() << "Should not have caught exception."; in TEST()
211 ADD_FAILURE() << "Should not have reached this line."; in TEST()
222 ADD_FAILURE() << "Should not have caught exception."; in TEST()
240 ADD_FAILURE() << "Should not have reached this line."; in TEST()
248 ADD_FAILURE() << "Should not have caught exception."; in TEST()
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| /openbmc/openbmc/meta-openembedded/meta-oe/licenses/ |
| H A D | GPL-2.0-with-lmbench-restriction | 9 or in any other way if you have modified the benchmarks.
14 If you have modifications or enhancements that you wish included in
26 b) Multiple times in the past people have wanted to report partial results.
32 c) We insist that if you formally report LMbench results, you have to
39 We have a lot of history with benchmarking and feel strongly that there
49 benchmarking systems out there that did what LMbench does and didn't have
70 see where tradeoffs may have been made. This is the driving force
93 lmbench numbers to show how your tweaks may (or may not) have
103 We have seen many cases in the past where partial or misleading
104 benchmark results have caused great harm to the community, and
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| /openbmc/openbmc/poky/bitbake/lib/toaster/tests/commands/ |
| H A D | test_loaddata.py | 26 "Loaded poky fixture but don't have a meta-poky for all releases"
32 # We only have the one layer for oe-core setup
35 "Loaded oe-core fixture but still have no openemebedded-core"
43 "Loaded settings but have no DEFAULT_RELEASE")
48 "Loaded settings but have no DEFCONF (default project "
|
| /openbmc/qemu/docs/devel/migration/ |
| H A D | compatibility.rst | 7 When we do migration, we have two QEMU processes: the source and the
12 There are two things that are different, but they have very similar
36 I am going to list the number of combinations that we can have. Let's
43 This have to work, and if it doesn't work it is a bug.
54 we have the same QEMU version in both sides (qemu-5.2) but we are using
62 both sides are the same QEMU and both sides have exactly the same
72 because we have the limitation than qemu-5.1 doesn't know pc-5.2. So
94 we have a problem when we try to migrate between different QEMU
120 hw_compat_X_Y is an array of registers that have the format:
134 queues to a device that have only one queue, we don't know where to
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| /openbmc/openbmc/meta-openembedded/meta-webserver/recipes-httpd/nginx/files/ |
| H A D | 0001-Allow-the-overriding-of-the-endianness-via-the-confi.patch | 26 + have=NGX_HAVE_LITTLE_ENDIAN . auto/have
49 - have=NGX_HAVE_LITTLE_ENDIAN . auto/have
56 + have=NGX_HAVE_LITTLE_ENDIAN . auto/have
|
| /openbmc/bmcweb/docs/ |
| H A D | OEM_SCHEMAS.md | 13 and can be maintained forever. Within OpenBMC, we have no such group of
36 have to break an API boundary to move to the standard implementation. Given the
41 their best to stay current on the evolving Redfish ecosystem, we have
48 systems. It's undesirable to have another company's, possibly a competitor, name
66 does not merge new schemas that have not been ratified by DMTF, feel free to
81 validator and should follow redfish API design practices. We require OEM to have
89 ''' There are organizations for which DMTF has a working relationship, and have
96 Given the nature of semantic versioning, Redfish does not directly have support
98 a version of the schemas that have been modified from the version available at
|
| /openbmc/u-boot/arch/mips/mach-bmips/ |
| H A D | Kconfig | 145 Comtrend AR-5315u boards have a BCM6318 SoC with 64 MB of RAM and 16
156 Comtrend AR-5387un boards have a BCM6328 SoC with 64 MB of RAM and 16
167 Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB
178 Comtrend VR-3032u boards have a BCM63268 SoC with 64 MB of RAM and
189 Comtrend WAP-5813n boards have a BCM6369 SoC with 64 MB of RAM and
200 Huawei EchoLife HG556a boards have a BCM6358 SoC with 64 MB of RAM
211 Netgear CG3100D boards have a BCM3380 SoC with 64 MB of RAM and 8 MB
222 Netgear DGND3700v2 boards have a BCM6362 SoC with 64 MB of RAM and
233 Sagem F@ST1704 boards have a BCM6338 SoC with 16 MB of RAM and 4 MB
244 SFR NeufBox 4 (Sercomm) boards have a BCM6358 SoC with 32 MB of RAM
|
| /openbmc/bmcweb/ |
| H A D | OWNERS | 5 # - Have a solid understanding of the bmcweb core code, and how it's used.
7 # - Have access to at least one upstream platform to test relevant patchsets.
18 # - Have an in-depth understanding of the Redfish standard, its constraints in
23 # - Be capable of, and have a track record of posing questions, clarifications,
26 # regularly attend the Redfish specification meetings to have a handle on
31 # - Have an understanding of, and track record of executing the various test
35 # - Have an understanding of DBus and the specific implementations of sdbusplus
53 # ideally should have a track record of doing it in the past.
|
| /openbmc/openbmc/poky/meta/files/common-licenses/ |
| H A D | SWL | 3 …HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DIS…
5 …have only "Restricted Rights" in the software and related documentation as defined in the Federal …
7 BY INSTALLING THIS SOFTWARE, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, THAT YOU UNDERSTAND…
|
| /openbmc/phosphor-power/phosphor-power-sequencer/test/ |
| H A D | config_file_parser_tests.cpp | 339 ADD_FAILURE() << "Should not have reached this line."; in TEST()
368 ADD_FAILURE() << "Should not have reached this line."; in TEST()
408 ADD_FAILURE() << "Should not have reached this line."; in TEST()
424 ADD_FAILURE() << "Should not have reached this line."; in TEST()
441 ADD_FAILURE() << "Should not have reached this line."; in TEST()
458 ADD_FAILURE() << "Should not have reached this line."; in TEST()
475 ADD_FAILURE() << "Should not have reached this line."; in TEST()
535 ADD_FAILURE() << "Should not have reached this line."; in TEST()
551 ADD_FAILURE() << "Should not have reached this line."; in TEST()
568 ADD_FAILURE() << "Should not have reached this line."; in TEST()
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| /openbmc/docs/designs/ |
| H A D | vpd-collection.md | 13 VPD, which the BMC currently does not support. Certain FRUs also have keyword
31 of certain parameters of the FRU (atypical - for FRUs that do not have an
43 For example, a single record can be used to group keywords that have similar
82 - If a FRU does not have a VPD store such as an EEPROM, the BMC should be able
97 - Applications on the BMC need to have the ability to query any given VPD
100 - Applications also need to have the ability to update the VPD contents in a
101 FRU. For example, the BMC needs to have the ability to update the system VPD
140 collect VPD. We could also have just a single rule, but that would mean we
141 would have to filter out non-VPD EEPROMs somehow.
153 record) which will have each keyword as a property (ex, FN, PN). This will
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| H A D | bmc-boot-ready.md | 23 services have completed running, there is a window there that a user could
35 There are three options that have been discussed to solve this issue:
44 applications have a mix of read-only properties (like current state) and
46 until everything is available could have unknown consequences. This also has
47 similar issues to option 2 in that applications and clients must have proper
89 been challenging. Some OpenBMC services have built in assumptions that the
90 multi-user.target and all of it's dependent services have completed prior to a
92 easier and safer to just have a global wait-for-bmc-ready function as proposed
|
| /openbmc/qemu/tests/qemu-iotests/ |
| H A D | 125 | 18 # You should have received a copy of the GNU General Public License
77 # write to an area that you have fallocated, no new blocks will have
85 # Write to something that in theory we have just fallocated
98 # size does not change if we have used preallocation.
140 # The image length should not have grown
145 # The host size should not have grown either
154 # The image length should not have grown
159 # The host size should not have grown either
185 # If the image does not have an external data file we can also verify its
186 # actual size. The resized image should have 7 clusters:
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | Kconfig | 55 If you have an ARM(R) platform with a Multimedia Card slot,
161 you are reading this help text, you most likely have no idea :-)
176 If you have an DAVINCI board with a Multimedia Card slot,
235 Multimedia Card Interface. If you have an i.MX or MPC512x platform
257 If you have an MMC controller on a PCI bus, say Y here.
267 If you have an omap2plus board with a Multimedia Card slot,
289 If you have a controller with this interface, say Y here.
333 If you have a BCM2835 platform with SD or MMC devices, say Y here.
360 If you have a controller with this interface, say Y here.
410 If you have a BCM2835 platform with SD or MMC devices,
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/ |
| H A D | iomux.h | 21 * - Each pad can have but not necessarily does have an output routing register
23 * - Each pad can have but not necessarily does have an input routing register
26 * The three register sets do not have a fixed offset to each other,
28 * have) and put the optional i/o routing registers into additional
|