Home
last modified time | relevance | path

Searched full:gpll (Results 1 – 25 of 39) sorted by relevance

12

/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rv1126.c24 gpll, enumerator
148 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
150 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
151 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
157 PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
158 PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
159 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
160 PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
161 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
167 PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
[all …]
H A Dclk-rv1108.c19 apll, dpll, gpll, enumerator
125 PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
126 PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
127 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
130 PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
131 PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
140 PNAME(mux_wifi_src_p) = { "gpll", "xin24m" };
141 PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" };
147 PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
150 PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" };
[all …]
H A Dclk-rk3036.c21 apll, dpll, gpll, enumerator
120 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
124 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
126 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
141 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
174 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
185 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
199 GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
449 * Make uart_pll_clk a child of the gpll, as all other sources are in rk3036_clk_init()
H A Dclk-rk3368.c17 apllb, aplll, dpll, cpll, gpll, npll, enumerator
97 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
98 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
99 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
100 PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
101 PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m",
103 PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
105 PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
106 PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
120 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy_480m" };
[all …]
H A Dclk-rk3399.c19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
134 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
135 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
136 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
137 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
138 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
139 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
141 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
143 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
[all …]
H A Dclk-rk3128.c18 apll, dpll, cpll, gpll, enumerator
135 PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
137 PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
138 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
139 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
141 PNAME(mux_clk_peri_src_p) = { "gpll", "cpll", "gpll_div2", "gpll_div3" };
142 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
144 PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
156 PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
165 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
[all …]
H A Dclk-rk3228.c19 apll, dpll, cpll, gpll, enumerator
141 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
142 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
143 PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
144 PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
146 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
147 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
149 PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
175 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
224 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
[all …]
H A Dclk-rk3188.c19 apll, cpll, dpll, gpll, enumerator
201 PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
202 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
203 PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
212 PNAME(mux_mac_p) = { "gpll", "dpll" };
222 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
233 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
280 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
298 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
669 "gpll", "cpll" };
[all …]
H A Dclk-rk3568.c23 apll, dpll, gpll, cpll, npll, vpll, enumerator
215 PNAME(mux_armclk_p) = { "apll", "gpll" };
236 PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
237 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
238 PNAME(npll_gpll_p) = { "npll", "gpll" };
239 PNAME(cpll_gpll_p) = { "cpll", "gpll" };
240 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
241 PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
242 PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
248 PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
[all …]
H A Dclk-rk3288.c24 apll, dpll, cpll, gpll, npll, enumerator
197 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
198 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
199 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
200 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
201 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
203 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
217 PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
222 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
232 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
[all …]
H A Dclk-px30.c22 gpll, enumerator
142 PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
145 PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
146 PNAME(mux_gpll_npll_p) = { "gpll", "npll" };
147 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
148 PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" };
149 PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" };
150 PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"};
162 PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" };
200 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0),
[all …]
H A Dclk-rk3328.c21 apll, dpll, cpll, gpll, npll, enumerator
145 PNAME(mux_2plls_p) = { "cpll", "gpll" };
146 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
147 PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
148 PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
149 PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
151 PNAME(mux_4plls_p) = { "cpll", "gpll",
154 PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
156 PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
224 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
[all …]
H A Dclk-rk3588.c41 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, enumerator
445 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
446 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
447 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
448 PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" };
449 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
450 PNAME(gpll_aupll_p) = { "gpll", "aupll" };
451 PNAME(gpll_lpll_p) = { "gpll", "lpll" };
452 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
453 PNAME(gpll_spll_p) = { "gpll", "spll" };
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c132 u32 apllb, aplll, dpll, cpll, gpll; in rkclk_init() local
139 * GPLL rate from the SPL stage. in rkclk_init()
141 rkclk_set_pll(cru, GPLL, &gpll_init_cfg); in rkclk_init()
149 gpll = rkclk_pll_get_rate(cru, GPLL); in rkclk_init()
151 debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n", in rkclk_init()
152 __func__, apllb, aplll, dpll, cpll, gpll); in rkclk_init()
179 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
354 * to select either CPLL or GPLL as the clock-parent. The location within
463 rate = rkclk_pll_get_rate(priv->cru, GPLL); in rk3368_clk_get_rate()
H A Dclk_rv1108.c450 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ in rv1108_i2c_set_clk()
514 debug("%s source gpll\n", __func__); in rv1108_mmc_set_clk()
631 unsigned int apll, dpll, gpll; in rkclk_init() local
651 gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); in rkclk_init()
656 printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll); in rkclk_init()
H A Dclk_rk3399.c556 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ in rk3399_i2c_set_clk()
595 * to select either CPLL or GPLL as the clock-parent. The location within
758 /* Select clk_sdmmc source from GPLL by default */ in rk3399_mmc_set_clk()
778 /* Select aclk_emmc source from GPLL */ in rk3399_mmc_set_clk()
787 /* Select clk_emmc source from GPLL too */ in rk3399_mmc_set_clk()
1112 /* configure gpll cpll */ in rkclk_init()
1156 /* perilp1 hclk select gpll as source */ in rkclk_init()
H A Dclk_rk3128.c178 * select gpll as pd_bus bus clock source and in rkclk_init()
201 * select gpll as pd_peri bus clock source and in rkclk_init()
H A Dclk_rk322x.c117 * select gpll as pd_bus bus clock source and in rkclk_init()
140 * select gpll as pd_peri bus clock source and in rkclk_init()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,px30-cru.yaml55 - const: gpll
115 clock-names = "xin24m", "gpll";
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
116 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
335 UNIPHIER_CLK_DIV("gpll", 4),
341 .parent_names = { "gpll/4", "ref", },
/openbmc/u-boot/board/rockchip/evb_rv1108/
H A DREADME37 APLL: 600000000 DPLL:792000000 GPLL:384000000
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rps_types.h95 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
H A Dintel_rps.c1363 /* RPS code assumes GPLL is used */ in chv_rps_enable()
1365 "GPLL not enabled\n"); in chv_rps_enable()
1367 drm_dbg(&i915->drm, "GPLL enabled? %s\n", in chv_rps_enable()
1422 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on in vlv_rps_min_freq()
1465 /* RPS code assumes GPLL is used */ in vlv_rps_enable()
1467 "GPLL not enabled\n"); in vlv_rps_enable()
1469 drm_dbg(&i915->drm, "GPLL enabled? %s\n", in vlv_rps_enable()
1612 * Slow = Fast = GPLL ref * N in byt_gpu_freq()
1626 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2 in chv_gpu_freq()
1676 vlv_get_cck_clock(i915, "GPLL ref", in vlv_init_gpll_ref_freq()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3368.h18 GPLL, enumerator
/openbmc/u-boot/drivers/spi/
H A Drk_spi.c212 * GPLL will be 576MHz, things will still work, as the in rockchip_spi_calc_modclk()
224 * speed of GPLL (594MHz) using an integer divider. in rockchip_spi_calc_modclk()

12