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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,pmic-mpp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC Multi-Purpose Pin (MPP) block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This binding describes the MPP block(s) found in the 8xxx series of
19 - items:
20 - enum:
21 - qcom,pm8019-mpp
[all …]
H A Dmarvell,orion-pinctrl.txt1 * Marvell Orion SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
13 contiguous MPP registers, and the second one describing the single
14 final MPP register, separated from the previous one.
16 Available mpp pins/groups and functions:
[all …]
H A Dmarvell,dove-pinctrl.txt1 * Marvell Dove SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
[all …]
H A Dmarvell,armada-375-pinctrl.txt1 * Marvell Armada 375 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
18 mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
19 mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
[all …]
H A Dmarvell,armada-xp-pinctrl.txt1 * Marvell Armada XP SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
14 Note: brackets (x) are not part of the mpp name for marvell,function and given
21 mpp0 0 gpio, ge0(txclkout), lcd(d0)
22 mpp1 1 gpio, ge0(txd0), lcd(d1)
23 mpp2 2 gpio, ge0(txd1), lcd(d2)
[all …]
H A Dmarvell,armada-370-pinctrl.txt1 * Marvell Armada 370 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 mpp0 0 gpio, uart0(rxd)
18 mpp2 2 gpio, i2c0(sck), uart0(txd)
19 mpp3 3 gpio, i2c0(sda), uart0(rxd)
20 mpp4 4 gpio, vdd(cpu-pd)
[all …]
H A Dmarvell,armada-38x-pinctrl.txt1 * Marvell Armada 380/385 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
13 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
[all …]
H A Dmarvell,armada-39x-pinctrl.txt1 * Marvell Armada 39x SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
13 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
[all …]
H A Dmarvell,armada-98dx3236-pinctrl.txt1 * Marvell 98dx3236 pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
15 mpp1 1 gpio, spi0(miso), dev(ad9)
17 mpp3 3 gpio, spi0(cs0), dev(ad11)
18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
19 mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
21 mpp7 7 gpio, sd0(d0), dev(ale0)
22 mpp8 8 gpio, sd0(d1), dev(ale1)
[all …]
/openbmc/linux/arch/arm/mach-dove/
H A Dmpp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-dove/mpp.c
5 * MPP functions for Marvell Dove SoCs
9 #include <linux/gpio.h>
11 #include <plat/mpp.h>
12 #include <plat/orion-gpio.h>
14 #include "mpp.h"
21 /* Map a group to a range of GPIO pins in that group */
45 /* Enable gpio for a range of pins. mode should be a combination of
55 /* Dump all the extra MPP registers. The platform code will dump the
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dorion5x-rd88f5182-nas.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "orion5x-mv88f5182.dtsi"
11 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
20 stdout-path = &uart0;
30 gpio-leds {
31 compatible = "gpio-leds";
32 pinctrl-0 = <&pmx_debug_led>;
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
33 * @mpp_get: (optional) special function to get mpp setting
34 * @mpp_set: (optional) special function to set mpp setting
35 * @mpp_gpio_req: (optional) special function to request gpio
36 * @mpp_gpio_dir: (optional) special function to set gpio direction
40 * between two or more different settings, e.g. assign mpp pin 13 to
45 * to allow pin settings with varying gpio pins.
[all …]
/openbmc/linux/arch/arm/plat-orion/
H A Dmpp.c2 * arch/arm/plat-orion/mpp.c
4 * MPP functions for Marvell orion SoCs
15 #include <linux/gpio.h>
16 #include <plat/orion-gpio.h>
17 #include <plat/mpp.h>
19 /* Address of the ith MPP control register */
34 printk(KERN_DEBUG "initial MPP regs:"); in orion_mpp_conf()
52 printk(KERN_ERR "orion_mpp_conf: invalid MPP " in orion_mpp_conf()
58 "orion_mpp_conf: requested MPP%u config " in orion_mpp_conf()
76 printk(KERN_DEBUG " final MPP regs:"); in orion_mpp_conf()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_sys_env_lib.c1 // SPDX-License-Identifier: GPL-2.0
28 return board_id & (MARVELL_BOARD_ID_MASK - 1); in mv_ddr_board_id_index_get()
32 * read gpio input for suspend-wakeup indication
34 * 0 - not supported,
35 * 1 - supported: read magic word detect wakeup,
36 * 2 - detected wakeup from gpio
40 u32 reg, board_id_index, gpio; in mv_ddr_sys_env_suspend_wakeup_check() local
46 printf("\n_failed loading Suspend-Wakeup information (invalid board ID)\n"); in mv_ddr_sys_env_suspend_wakeup_check()
51 * - Detect if Suspend-Wakeup is supported on current board in mv_ddr_sys_env_suspend_wakeup_check()
52 * - Fetch the GPIO number for wakeup status input indication in mv_ddr_sys_env_suspend_wakeup_check()
[all …]
/openbmc/linux/arch/arm/mach-mv78xx0/
H A Dmpp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-mv78x00/mpp.c
5 * MPP functions for Marvell MV78x00 SoCs
7 #include <linux/gpio.h>
11 #include <plat/mpp.h>
14 #include "mpp.h"
25 printk(KERN_ERR "MPP setup: unknown mv78x00 variant " in mv78xx0_variant()
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-ssbi-mpp.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/gpio/driver.h>
17 #include <linux/pinctrl/pinconf-generic.h>
22 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
25 #include "../pinctrl-utils.h"
27 /* MPP registers */
31 /* MPP Type: type */
90 * struct pm8xxx_pin_data - dynamic configuration for a pin
96 * @paired: mpp operates in paired mode
97 * @output_value: logical output value of the mpp
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,mvebu-pinctrl.txt1 The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
2 pins (mpp) to a specific function.
5 mpp pins or group of pins and a mpp function common to all pins.
8 - compatible: "marvell,mvebu-pinctrl",
9 "marvell,ap806-pinctrl",
10 "marvell,armada-7k-pinctrl",
11 "marvell,armada-8k-cpm-pinctrl",
12 "marvell,armada-8k-cps-pinctrl"
13 - bank-name: A string defining the pinc controller bank name
14 - reg: A pair of values defining the pin controller base address
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dpmi8994.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/spmi/spmi.h>
8 compatible = "qcom,pmi8994", "qcom,spmi-pmic";
10 #address-cells = <1>;
11 #size-cells = <0>;
13 pmi8994_gpios: gpio@c000 {
14 compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
16 gpio-controller;
17 gpio-ranges = <&pmi8994_gpios 0 0 10>;
[all …]
H A Dpm8950.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/iio/qcom,spmi-vadc.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
12 #include <dt-bindings/spmi/spmi.h>
16 compatible = "qcom,pm8950", "qcom,spmi-pmic";
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "qcom,pm8916-pon";
[all …]
H A Dpmi8950.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/iio/qcom,spmi-vadc.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/spmi/spmi.h>
10 compatible = "qcom,pmi8950", "qcom,spmi-pmic";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "qcom,spmi-vadc";
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dpma8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/spmi/spmi.h>
9 compatible = "qcom,pma8084", "qcom,spmi-pmic";
11 #address-cells = <1>;
12 #size-cells = <0>;
15 compatible = "qcom,pm8941-rtc";
18 reg-names = "rtc", "alarm";
23 compatible = "qcom,pm8941-pwrkey";
[all …]
H A Dpm8841.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/spmi/spmi.h>
7 thermal-zones {
8 pm8841-thermal {
9 polling-delay-passive = <100>;
10 polling-delay = <0>;
11 thermal-sensors = <&pm8841_temp>;
39 compatible = "qcom,pm8841", "qcom,spmi-pmic";
41 #address-cells = <1>;
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dsys_env_lib.c1 // SPDX-License-Identifier: GPL-2.0
41 u32 g_dev_id = -1;
78 return board_id & (MARVELL_BOARD_ID_MASK - 1); in mv_board_id_index_get()
83 * DESCRIPTION: Reads GPIO input for suspend-wakeup indication.
87 * 0 - Not supported,
88 * 1 - supported: read magic word detect wakeup,
89 * 2 - detected wakeup from GPIO.
93 u32 reg, board_id_index, gpio; in sys_env_suspend_wakeup_check() local
99 printf("\n_failed loading Suspend-Wakeup information (invalid board ID)\n"); in sys_env_suspend_wakeup_check()
104 * - Detect if Suspend-Wakeup is supported on current board in sys_env_suspend_wakeup_check()
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dts209-setup.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * QNAP TS-109/TS-209 Board Setup
7 #include <linux/gpio.h>
21 #include <asm/mach-types.h>
25 #include "mpp.h"
27 #include "tsx09-common.h"
38 * [2] 0x00000000-0x00200000 : "Kernel"
39 * [3] 0x00200000-0x00600000 : "RootFS1"
40 * [4] 0x00600000-0x00700000 : "RootFS2"
41 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
19 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
[all …]

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