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/openbmc/linux/drivers/gpio/
H A Dgpio-en7523.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/gpio/driver.h>
15 * airoha_gpio_ctrl - Airoha GPIO driver data
34 static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio, in airoha_dir_set() argument
37 struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); in airoha_dir_set() local
38 u32 dir = ioread32(ctrl->dir[gpio / 16]); in airoha_dir_set()
39 u32 output = ioread32(ctrl->output); in airoha_dir_set()
40 u32 mask = BIT((gpio % 16) * 2); in airoha_dir_set()
44 output |= BIT(gpio); in airoha_dir_set()
47 output &= ~BIT(gpio); in airoha_dir_set()
[all …]
H A Dgpio-idt3243x.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/gpio/driver.h>
23 void __iomem *gpio; member
30 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); in idt_gpio_dispatch() local
37 pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND); in idt_gpio_dispatch()
38 pending &= ~ctrl->mask_cache; in idt_gpio_dispatch()
39 for_each_set_bit(bit, &pending, gc->ngpio) { in idt_gpio_dispatch()
40 virq = irq_linear_revmap(gc->irq.domain, bit); in idt_gpio_dispatch()
51 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); in idt_gpio_irq_set_type() local
58 return -EINVAL; in idt_gpio_irq_set_type()
[all …]
H A Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/gpio/driver.h>
29 /* Two bits per GPIO in IMR registers */
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
45 * @base: Base address of the register block for a GPIO bank
49 * @bank_read: Read a bank setting as a single 32-bit value
50 * @bank_write: Write a bank setting as a single 32-bit value
53 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55 * a value from (to) these registers. The IMR register consists of four 16-bit
[all …]
H A Dgpio-ath79.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Atheros AR71XX/AR724X/AR913X GPIO API support
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
11 #include <linux/gpio/driver.h>
13 #include <linux/platform_data/gpio-ath79.h>
44 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) in ath79_gpio_read() argument
46 return readl(ctrl->base + reg); in ath79_gpio_read()
49 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, in ath79_gpio_write() argument
52 writel(val, ctrl->base + reg); in ath79_gpio_write()
[all …]
H A Dgpio-omap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support functions for OMAP GPIO
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 #include <linux/gpio/driver.h>
27 #include <linux/platform_data/gpio-omap.h>
36 u32 ctrl; member
78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs35l45.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
11 - Richard Fitzgerald <rf@opensource.cirrus.com>
18 - $ref: dai-common.yaml#
23 - cirrus,cs35l45
28 '#sound-dai-cells':
31 reset-gpios:
34 vdd-a-supply:
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/openbmc/linux/drivers/net/mdio/
H A Dmdio-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO based MDIO bitbang driver.
7 * by Laurent Pinchart <laurentp@cse-semaphore.com>
20 #include <linux/gpio/consumer.h>
22 #include <linux/mdio-bitbang.h>
23 #include <linux/mdio-gpio.h>
26 #include <linux/platform_data/mdio-gpio.h>
31 struct mdiobb_ctrl ctrl; member
38 bitbang->mdc = devm_gpiod_get_index(dev, NULL, MDIO_GPIO_MDC, in mdio_gpio_get_data()
40 if (IS_ERR(bitbang->mdc)) in mdio_gpio_get_data()
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-iomega_ix2_200.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
8 model = "Iomega StorCenter ix2-200";
9 compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
33 pinctrl-names = "default";
35 pmx_button_reset: pmx-button-reset {
[all …]
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
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/openbmc/linux/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5249.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * mcf5249.h -- Definitions for Motorola Coldfire 5249
30 #define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
31 #define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
47 #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
49 #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
51 #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
52 #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
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/openbmc/u-boot/board/freescale/m5373evb/
H A Dnand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
22 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) in nand_hwcontrol() argument
27 if (ctrl & NAND_CTRL_CHANGE) { in nand_hwcontrol()
28 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; in nand_hwcontrol()
32 if (ctrl & NAND_NCE) in nand_hwcontrol()
37 if (ctrl & NAND_CLE) in nand_hwcontrol()
39 if (ctrl & NAND_ALE) in nand_hwcontrol()
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/openbmc/u-boot/board/freescale/m5329evb/
H A Dnand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
22 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) in nand_hwcontrol() argument
27 if (ctrl & NAND_CTRL_CHANGE) { in nand_hwcontrol()
28 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; in nand_hwcontrol()
32 if (ctrl & NAND_NCE) in nand_hwcontrol()
37 if (ctrl & NAND_CLE) in nand_hwcontrol()
39 if (ctrl & NAND_ALE) in nand_hwcontrol()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/leds/
H A Dkinetic,ktd2692.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markuss Broks <markuss.broks@gmail.com>
13 KTD2692 is the ideal power solution for high-power flash LEDs.
14 It uses ExpressWire single-wire programming for maximum flexibility.
16 The ExpressWire interface through CTRL pin can control LED on/off and
20 Also, When the AUX pin is pulled high while CTRL pin is high,
21 LED current will be ramped up to the flash-mode current level.
27 ctrl-gpios:
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/openbmc/linux/Documentation/devicetree/bindings/iio/amplifiers/
H A Dadi,hmc425a.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HMC425A 6-bit Digital Step Attenuator
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Digital Step Attenuator IIO device with gpio interface.
14 HMC425A 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz
15 https://www.analog.com/media/en/technical-documentation/data-sheets/hmc425A.pdf
20 - adi,hmc425a
22 vcc-supply: true
[all …]
/openbmc/u-boot/board/ti/panda/
H A Dpanda.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/mach-types.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/gpio.h>
21 #include <asm/ehci-omap.h>
48 gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA; in board_init()
49 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ in board_init()
61 * Description: Detect if we are running on a panda revision A1-A6,
66 * GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
80 /* Setup the mux for the common board ID pins (gpio 171 and 182) */ in get_board_revision()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm525xsim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
44 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
45 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
46 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
47 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
48 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
35 * @mpp_gpio_req: (optional) special function to request gpio
36 * @mpp_gpio_dir: (optional) special function to set gpio direction
45 * to allow pin settings with varying gpio pins.
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
63 * @val: ctrl setting value
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
[all …]
/openbmc/linux/drivers/staging/sm750fb/
H A Dddk750_power.c1 // SPDX-License-Identifier: GPL-2.0
34 unsigned int ctrl = 0; in sm750_set_power_mode() local
36 ctrl = peek32(POWER_MODE_CTRL) & ~POWER_MODE_CTRL_MODE_MASK; in sm750_set_power_mode()
43 ctrl |= POWER_MODE_CTRL_MODE_MODE0; in sm750_set_power_mode()
47 ctrl |= POWER_MODE_CTRL_MODE_MODE1; in sm750_set_power_mode()
51 ctrl |= POWER_MODE_CTRL_MODE_SLEEP; in sm750_set_power_mode()
60 ctrl &= ~POWER_MODE_CTRL_OSC_INPUT; in sm750_set_power_mode()
62 ctrl &= ~POWER_MODE_CTRL_336CLK; in sm750_set_power_mode()
65 ctrl |= POWER_MODE_CTRL_OSC_INPUT; in sm750_set_power_mode()
67 ctrl |= POWER_MODE_CTRL_336CLK; in sm750_set_power_mode()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dbrcm,ns2-drd-phy.txt4 - compatible: brcm,ns2-drd-phy
5 - reg: offset and length of the NS2 PHY related registers.
6 - reg-names
8 icfg - for DRD ICFG configurations
9 rst-ctrl - for DRD IDM reset
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11 usb2-strap - for port over current polarity reversal
12 - #phy-cells: Must be 0. No args required.
13 - vbus-gpios: vbus gpio binding
14 - id-gpios: id gpio binding
[all …]
/openbmc/openbmc/meta-google/recipes-google/gpio/
H A Dgpio-ctrl_git.bb1 SUMMARY = "GPIO control library for bash scripts"
2 DESCRIPTION = "GPIO control library for bash scripts."
3 LICENSE = "Apache-2.0"
4 LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/Apache-2.0;md5=89aea4e17d99a7cacd…
12 install -d ${D}${datadir}/gpio-ctrl
13 install -m 0755 ${UNPACKDIR}/lib.sh ${D}${datadir}/gpio-ctrl/
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-lpass-lpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
9 #include <linux/gpio/driver.h>
15 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
21 #include "pinctrl-lpass-lpi.h"
29 struct pinctrl_dev *ctrl; member
44 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_read()
50 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_write()
67 return pctrl->data->nfunctions; in lpi_gpio_get_functions_count()
[all …]
/openbmc/linux/drivers/watchdog/
H A Dit87_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * for ITE IT87xx Environment Control - Low Pin Count Input / Output
12 * Data-sheets: Publicly available at the ITE website
46 #define GPIO 0x07 macro
83 /* GPIO Configuration Registers LDN=0x07 */
89 /* GPIO Bits WDTCFG */
120 return -EBUSY; in superio_enter()
164 /* Internal function, should be called after superio_select(GPIO) */
194 superio_select(GPIO); in wdt_update_timeout()
204 t -= t % 60; in wdt_round_time()
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/openbmc/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
H A Dgpio_public.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /*! Write to a control register of GPIO[ID]
23 \param ID[in] GPIO identifier
27 \return none, GPIO[ID].ctrl[reg] = value
34 /*! Read from a control register of GPIO[ID]
36 \param ID[in] GPIO identifier
40 \return GPIO[ID].ctrl[reg]
/openbmc/u-boot/arch/arm/dts/
H A Ddm816x.dtsi7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/omap.h>
12 interrupt-parent = <&intc>;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
31 compatible = "arm,cortex-a8";
38 compatible = "arm,cortex-a8-pmu";
47 compatible = "ti,omap-infra";
[all …]

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