Home
last modified time | relevance | path

Searched +full:gpio +full:- +full:0 (Results 1 – 25 of 1222) sorted by relevance

12345678910>>...49

/openbmc/linux/arch/arc/boot/dts/
H A Dabilis_tb101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
H A Dabilis_tb100.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos4x12-pinctrl.dtsi2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
[all …]
H A Dexynos4210-pinctrl.dtsi2 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
4 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2011-2012 Linaro Ltd.
9 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
20 gpio-controller;
21 #gpio-cells = <2>;
23 interrupt-controller;
24 #interrupt-cells = <2>;
28 gpio-controller;
29 #gpio-cells = <2>;
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dpxaregs.c2 * pxaregs - tool to display and modify PXA250's registers at runtime
4 * (c) Copyright 2002 by M&N Logistik-Lösungen Online GmbH
9 * Please send patches to h.schurig, working at mn-logistik.de
10 * - added fix from Bernhard Nemec
11 * - i2c registers from Stefan Eletzhofer
25 #include <linux/i2c-dev.h>
29 static int fd = -1;
44 { "IBMR", 0x40301680, 0, 0xffffffff, 'x', "I2C Bus Monitor Register" },
45 { "IBMR_SDAS", 0x40301680, 0, 0x00000001, 'x', "SDA Status" },
46 { "IBMR_SCLS", 0x40301680, 1, 0x00000001, 'x', "SDA Status" },
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
8 properties, each containing a 'gpio-list':
10 gpio-list ::= <single-gpio> [gpio-list]
11 single-gpio ::= <gpio-phandle> <gpio-specifier>
12 gpio-phandle : phandle to gpio controller node
13 gpio-specifier : Array of #gpio-cells specifying specific gpio
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
21 GPIO properties can contain one or more GPIO phandles, but only in exceptional
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-ep9301.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-ep9301.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EP93xx GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
12 - Nikita Shubin <nikita.shubin@maquefel.me>
17 - const: cirrus,ep9301-gpio
18 - items:
[all …]
H A Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/aspeed.h>
10 #include <linux/gpio/driver.h>
25 * These two headers aren't meant to be used by GPIO drivers. We need
30 #include <linux/gpio/consumer.h>
50 * represents disabled debouncing for the GPIO. Any other value for an element
72 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
73 * +4: Rd/Wr: Direction (0=in, 1=out)
85 * line even when the GPIO is configured as an output. Since
94 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
[all …]
H A Dgpio-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2022 NVIDIA Corporation
9 #include <linux/gpio/driver.h>
18 #include <dt-bindings/gpio/tegra186-gpio.h>
19 #include <dt-bindings/gpio/tegra194-gpio.h>
20 #include <dt-bindings/gpio/tegra234-gpio.h>
21 #include <dt-bindings/gpio/tegra241-gpio.h>
24 #define TEGRA186_GPIO_CTL_SCR 0x0c
28 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
30 #define TEGRA186_GPIO_VM 0x00
[all …]
H A Dgpio-dwapb.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/gpio/driver.h>
25 #include "gpiolib-acpi.h"
27 #define GPIO_SWPORTA_DR 0x00
28 #define GPIO_SWPORTA_DDR 0x04
29 #define GPIO_SWPORTB_DR 0x0c
30 #define GPIO_SWPORTB_DDR 0x10
31 #define GPIO_SWPORTC_DR 0x18
32 #define GPIO_SWPORTC_DDR 0x1c
33 #define GPIO_SWPORTD_DR 0x24
[all …]
H A Dgpio-npcm-sgpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Nuvoton NPCM Serial GPIO Driver
10 #include <linux/gpio/driver.h>
22 #define NPCM_IOXCFG1 0x2A
23 #define NPCM_IOXCFG1_SFT_CLK GENMASK(3, 0)
27 #define NPCM_IOXCTS 0x28
32 #define NPCM_IOXCFG2 0x2B
33 #define NPCM_IOXCFG2_PORT GENMASK(3, 0)
35 #define NPCM_IXOEVCFG_MASK GENMASK(1, 0)
37 #define NPCM_IXOEVCFG_RISING BIT(0)
[all …]
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dadi_gpio2.c5 * Copyright 2008-2013 Analog Devices Inc.
7 * Licensed under the GPL-2 or later
12 #include <asm/gpio.h>
20 static void gpio_error(unsigned gpio) in gpio_error() argument
22 printf("adi_gpio2: GPIO %d wasn't requested!\n", gpio); in gpio_error()
30 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; in set_label()
42 printf("adi_gpio2: please provide none-null label\n"); in cmp_label()
47 return -EINVAL; in cmp_label()
56 static DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
59 inline int check_gpio(unsigned gpio) in check_gpio() argument
[all …]
H A Dmpc83xx_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale MPC83xx GPIO handling.
8 #include <asm/gpio.h>
12 #define CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION 0
15 #define CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION 0
18 #define CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0
21 #define CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0
24 #define CONFIG_MPC83XX_GPIO_0_INIT_VALUE 0
27 #define CONFIG_MPC83XX_GPIO_1_INIT_VALUE 0
36 int gpio_request(unsigned gpio, const char *label) in gpio_request() argument
[all …]
H A Dtegra_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NVIDIA Tegra20 GPIO handling.
4 * (C) Copyright 2010-2012,2015
21 #include <asm/gpio.h>
22 #include <dm/device-internal.h>
23 #include <dt-bindings/gpio/gpio.h>
25 static const int CONFIG_SFIO = 0;
27 static const int DIRECTION_INPUT = 0;
33 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
36 /* Information about each port at run-time */
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-yosemite4.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/leds/leds-pca955x.h>
8 #include <dt-bindings/i2c/i2c.h>
12 compatible = "facebook,yosemite4-bmc", "aspeed,ast2600";
44 stdout-path = "serial4:57600n8";
49 reg = <0x80000000 0x80000000>;
52 iio-hwmon {
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_gpio-test.c2 * QTest testcase for the Nuvoton NPCM7xx GPIO modules.
18 #include "libqtest-single.h"
21 #define GPIO(x) (0xf0010000 + (x) * 0x1000) macro
24 /* GPIO registers */
25 #define GP_N_TLOCK1 0x00
26 #define GP_N_DIN 0x04 /* Data IN */
27 #define GP_N_POL 0x08 /* Polarity */
28 #define GP_N_DOUT 0x0c /* Data OUT */
29 #define GP_N_OE 0x10 /* Output Enable */
30 #define GP_N_OTYP 0x14
[all …]
H A Dstm32l4x5_gpio-test.c4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
15 #define GPIO_BASE_ADDR 0x48000000
16 #define GPIO_SIZE 0x400
20 #define GPIO_A 0x48000000
21 #define GPIO_B 0x48000400
22 #define GPIO_C 0x48000800
23 #define GPIO_D 0x48000C00
[all …]
/openbmc/openbmc/meta-yadro/meta-nicole/recipes-bsp/u-boot/files/
H A D0003-aspeed-add-gpio-support.patch4 Subject: [PATCH] aspeed: add gpio support
6 This is an initial support for the parallel GPIO pins directly connected
9 This brings the functions and a shell command to manipulate the GPIO
10 state. The GPIO value reading and writing work in non interrupt mode
13 Signed-off-by: Alexander Filippov <a.filippov@yadro.com>
14 ---
15 arch/arm/include/asm/arch-aspeed/gpio.h | 65 ++++
16 arch/arm/include/asm/arch-aspeed/platform.h | 1 +
17 drivers/gpio/Makefile | 2 +
18 drivers/gpio/aspeed_gpio.c | 386 ++++++++++++++++++++
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmucmc52.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2006-2007 Secret Lab Technologies Ltd.
12 /* Timer pins that need to be in GPIO mode */
13 &gpt0 { gpio-controller; };
14 &gpt1 { gpio-controller; };
15 &gpt2 { gpio-controller; };
16 &gpt3 { gpio-controller; };
50 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
[all …]
/openbmc/linux/arch/mips/include/asm/mach-au1x00/
H A Dgpio-au1000.h2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
12 #include <asm/mach-au1x00/au1000.h>
14 /* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
17 #define ALCHEMY_GPIO1_BASE 0
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
28 #define AU1000_SYS_TRIOUTRD 0x100
29 #define AU1000_SYS_TRIOUTCLR 0x100
30 #define AU1000_SYS_OUTPUTRD 0x108
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #define MFP_PIN_PXA300(gpio) \ argument
6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
11 #define MFP_PIN_PXA300_2(gpio) \ argument
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dcpu_init.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
31 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); in init_fbcs()
32 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); in init_fbcs()
33 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); in init_fbcs()
39 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); in init_fbcs()
40 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); in init_fbcs()
41 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); in init_fbcs()
[all …]
/openbmc/skeleton/libopenbmc_intf/
H A Dgpio.c14 #include "gpio.h"
18 #include <linux/gpio.h>
21 #define GPIO_BASE_PATH "/sys/class/gpio"
26 int gpio_write(GPIO* gpio, uint8_t value) in gpio_write() argument
28 g_assert (gpio != NULL); in gpio_write()
30 memset(&data, 0, sizeof(data)); in gpio_write()
31 data.values[0] = value; in gpio_write()
33 if (gpio->fd <= 0) in gpio_write()
38 if (ioctl(gpio->fd, GPIOHANDLE_SET_LINE_VALUES_IOCTL, &data) < 0) in gpio_write()
46 int gpio_read(GPIO* gpio, uint8_t *value) in gpio_read() argument
[all …]

12345678910>>...49