| /openbmc/u-boot/arch/arm/dts/ |
| H A D | exynos4x12-pinctrl.dtsi | 2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
[all …]
|
| H A D | exynos4210-pinctrl.dtsi | 2 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
4 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2011-2012 Linaro Ltd.
9 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
20 gpio-controller;
21 #gpio-cells = <2>;
23 interrupt-controller;
24 #interrupt-cells = <2>;
28 gpio-controller;
29 #gpio-cells = <2>;
[all …]
|
| H A D | keystone-k2hk.dtsi | 2 * Copyright 2013-2014 Texas Instruments, Inc.
13 #address-cells = <1>;
14 #size-cells = <0>;
16 interrupt-parent = <&gic>;
18 cpu@0 {
19 compatible = "arm,cortex-a15";
21 reg = <0>;
25 compatible = "arm,cortex-a15";
31 compatible = "arm,cortex-a15";
37 compatible = "arm,cortex-a15";
[all …]
|
| H A D | stm32h743-pinctrl.dtsi | 2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
47 pin-controller {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stm32h743-pinctrl";
51 ranges = <0 0x58020000 0x3000>;
52 pins-are-numbered;
54 gpioa: gpio@58020000 {
[all …]
|
| H A D | exynos5250-pinctrl.dtsi | 2 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
[all …]
|
| H A D | imx53.dtsi | 10 * http://www.opensource.org/licenses/gpl-license.html
15 #include "imx53-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
38 tzic: tz-interrupt-controller@fffc000 {
39 compatible = "fsl,imx53-tzic", "fsl,tzic";
40 interrupt-controller;
41 #interrupt-cells = <1>;
[all …]
|
| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | gpio.txt | 1 Specifying GPIO information for devices
5 -----------------
8 properties, each containing a 'gpio-list':
10 gpio-list ::= <single-gpio> [gpio-list]
11 single-gpio ::= <gpio-phandle> <gpio-specifier>
12 gpio-phandle : phandle to gpio controller node
13 gpio-specifier : Array of #gpio-cells specifying specific gpio
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
21 GPIO properties can contain one or more GPIO phandles, but only in exceptional
[all …]
|
| H A D | snps,creg-gpio.txt | 1 GPIO via CREG (control registers) driver
3 31 9 7 5 0 < bit number
5 [ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register
8 write 0x2 == set output to "1" (activate)
9 write 0x3 == set output to "0" (deactivate)
12 - compatible : "snps,creg-gpio"
13 - reg : Exactly one register range with length 0x4.
14 - #gpio-cells : Should be one - the pin number.
15 - gpio-controller : Marks the device node as a GPIO controller.
16 - gpio-count: Number of GPIO pins.
[all …]
|
| H A D | nvidia,tegra186-gpio.txt | 1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
27 documentation for rationale. Any particular GPIO client is expected to access
[all …]
|
| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/ |
| H A D | pxaregs.c | 2 * pxaregs - tool to display and modify PXA250's registers at runtime
4 * (c) Copyright 2002 by M&N Logistik-Lösungen Online GmbH
9 * Please send patches to h.schurig, working at mn-logistik.de
10 * - added fix from Bernhard Nemec
11 * - i2c registers from Stefan Eletzhofer
25 #include <linux/i2c-dev.h>
29 static int fd = -1;
44 { "IBMR", 0x40301680, 0, 0xffffffff, 'x', "I2C Bus Monitor Register" },
45 { "IBMR_SDAS", 0x40301680, 0, 0x00000001, 'x', "SDA Status" },
46 { "IBMR_SCLS", 0x40301680, 1, 0x00000001, 'x', "SDA Status" },
[all …]
|
| /openbmc/u-boot/drivers/gpio/ |
| H A D | adi_gpio2.c | 5 * Copyright 2008-2013 Analog Devices Inc.
7 * Licensed under the GPL-2 or later
12 #include <asm/gpio.h>
20 static void gpio_error(unsigned gpio) in gpio_error() argument
22 printf("adi_gpio2: GPIO %d wasn't requested!\n", gpio); in gpio_error()
30 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; in set_label()
42 printf("adi_gpio2: please provide none-null label\n"); in cmp_label()
47 return -EINVAL; in cmp_label()
56 static DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
59 inline int check_gpio(unsigned gpio) in check_gpio() argument
[all …]
|
| H A D | mpc83xx_gpio.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale MPC83xx GPIO handling.
8 #include <asm/gpio.h>
12 #define CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION 0
15 #define CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION 0
18 #define CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0
21 #define CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0
24 #define CONFIG_MPC83XX_GPIO_0_INIT_VALUE 0
27 #define CONFIG_MPC83XX_GPIO_1_INIT_VALUE 0
36 int gpio_request(unsigned gpio, const char *label) in gpio_request() argument
[all …]
|
| H A D | tegra_gpio.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * NVIDIA Tegra20 GPIO handling.
4 * (C) Copyright 2010-2012,2015
21 #include <asm/gpio.h>
22 #include <dm/device-internal.h>
23 #include <dt-bindings/gpio/gpio.h>
25 static const int CONFIG_SFIO = 0;
27 static const int DIRECTION_INPUT = 0;
33 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
36 /* Information about each port at run-time */
[all …]
|
| H A D | omap_gpio.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
13 * linux/arch/arm/plat-omap/gpio.c
15 * Support functions for OMAP GPIO
17 * Copyright (C) 2003-2005 Nokia Corporation
23 #include <asm/gpio.h>
30 #define OMAP_GPIO_DIR_OUT 0
44 static inline int get_gpio_index(int gpio) in get_gpio_index() argument
46 return gpio & 0x1f; in get_gpio_index()
49 int gpio_is_valid(int gpio) in gpio_is_valid() argument
[all …]
|
| H A D | s5p_gpio.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/gpio.h>
14 #include <dm/device-internal.h>
20 #define CON_MASK(val) (0xf << ((val) << 2))
21 #define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2)) argument
22 #define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2)) argument
24 #define DAT_MASK(gpio) (0x1 << (gpio)) argument
25 #define DAT_SET(gpio) (0x1 << (gpio)) argument
27 #define PULL_MASK(gpio) (0x3 << ((gpio) << 1)) argument
28 #define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1)) argument
[all …]
|
| /openbmc/openbmc/meta-yadro/meta-nicole/recipes-bsp/u-boot/files/ |
| H A D | 0003-aspeed-add-gpio-support.patch | 4 Subject: [PATCH] aspeed: add gpio support
6 This is an initial support for the parallel GPIO pins directly connected
9 This brings the functions and a shell command to manipulate the GPIO
10 state. The GPIO value reading and writing work in non interrupt mode
13 Signed-off-by: Alexander Filippov <a.filippov@yadro.com>
14 ---
15 arch/arm/include/asm/arch-aspeed/gpio.h | 65 ++++
16 arch/arm/include/asm/arch-aspeed/platform.h | 1 +
17 drivers/gpio/Makefile | 2 +
18 drivers/gpio/aspeed_gpio.c | 386 ++++++++++++++++++++
[all …]
|
| /openbmc/qemu/tests/qtest/ |
| H A D | npcm7xx_gpio-test.c | 2 * QTest testcase for the Nuvoton NPCM7xx GPIO modules.
18 #include "libqtest-single.h"
21 #define GPIO(x) (0xf0010000 + (x) * 0x1000) macro
24 /* GPIO registers */
25 #define GP_N_TLOCK1 0x00
26 #define GP_N_DIN 0x04 /* Data IN */
27 #define GP_N_POL 0x08 /* Polarity */
28 #define GP_N_DOUT 0x0c /* Data OUT */
29 #define GP_N_OE 0x10 /* Output Enable */
30 #define GP_N_OTYP 0x14
[all …]
|
| H A D | stm32l4x5_gpio-test.c | 4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
15 #define GPIO_BASE_ADDR 0x48000000
16 #define GPIO_SIZE 0x400
20 #define GPIO_A 0x48000000
21 #define GPIO_B 0x48000400
22 #define GPIO_C 0x48000800
23 #define GPIO_D 0x48000C00
[all …]
|
| /openbmc/skeleton/libopenbmc_intf/ |
| H A D | gpio.c | 14 #include "gpio.h"
18 #include <linux/gpio.h>
21 #define GPIO_BASE_PATH "/sys/class/gpio"
26 int gpio_write(GPIO* gpio, uint8_t value) in gpio_write() argument
28 g_assert (gpio != NULL); in gpio_write()
30 memset(&data, 0, sizeof(data)); in gpio_write()
31 data.values[0] = value; in gpio_write()
33 if (gpio->fd <= 0) in gpio_write()
38 if (ioctl(gpio->fd, GPIOHANDLE_SET_LINE_VALUES_IOCTL, &data) < 0) in gpio_write()
46 int gpio_read(GPIO* gpio, uint8_t *value) in gpio_read() argument
[all …]
|
| /openbmc/u-boot/arch/m68k/cpu/mcf5445x/ |
| H A D | cpu_init.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
31 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); in init_fbcs()
32 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); in init_fbcs()
33 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); in init_fbcs()
39 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); in init_fbcs()
40 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); in init_fbcs()
41 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); in init_fbcs()
[all …]
|
| /openbmc/u-boot/arch/mips/dts/ |
| H A D | pic32mzda.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/microchip,clock.h>
9 #include <dt-bindings/gpio/gpio.h>
29 cpu@0 {
35 compatible = "microchip,pic32mzda-clk";
36 reg = <0x1f801200 0x1000>;
37 #clock-cells = <1>;
41 compatible = "microchip,pic32mzda-uart";
42 reg = <0x1f822000 0x50>;
[all …]
|
| /openbmc/openbmc/meta-ibm/recipes-phosphor/power/power-sequencer/swift/ |
| H A D | ucd90160.yaml | 1 - Device:
2 index: 0
3 # Linux sysfs path for this power sequencer (0xC8 8-bit address)
4 path: /sys/bus/i2c/devices/i2c-8/8-0064
6 - "12.0V"
7 - "3.3V"
8 - "1.8V"
9 - "1.1V"
10 - "0.8V_SW"
11 - "5.0V"
[all …]
|
| /openbmc/u-boot/doc/device-tree-bindings/pinctrl/ |
| H A D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and GPIO controller
3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
6 GPIO and pin controller:
7 ------------------------
11 Refer to pinctrl-bindings.txt in this directory for details of the
17 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
19 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
28 - pins 20-24
[all …]
|
| /openbmc/openbmc/meta-facebook/meta-tiogapass/recipes-phosphor/flash/phosphor-software-manager/ |
| H A D | bios-update | 3 set -e
5 POWER_CMD="/usr/sbin/power-util mb"
7 GPIO=389
13 ME_CMD_RECOVER="1 0x2e 0 0xdf 4 0x57 0x01 0x00 0x01"
14 ME_CMD_RESET="1 6 0 0x2 0"
16 SPI_PATH="/sys/bus/platform/drivers/aspeed-smc"
20 echo "switch bios GPIO to bmc"
21 if [ ! -d /sys/class/gpio/gpio$GPIO ]; then
22 cd /sys/class/gpio
23 echo $GPIO > "export"
[all …]
|
| /openbmc/u-boot/board/renesas/sh7753evb/ |
| H A D | sh7753evb.c | 1 // SPDX-License-Identifier: GPL-2.0+
19 return 0; in checkboard()
24 struct gpio_regs *gpio = GPIO_BASE; in init_gpio() local
27 /* GPIO */ in init_gpio()
28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0x0000, &gpio->pdcr); /* SPI0 */ in init_gpio()
32 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
33 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
[all …]
|