Home
last modified time | relevance | path

Searched +full:gp +full:- +full:pwm3 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
/openbmc/u-boot/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-37xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot Marvell 37xx SoC pinctrl driver
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
13 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
22 #include <dm/device-internal.h>
160 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
214 *offset -= GPIO_PER_REG; in armada_37xx_update_reg()
224 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) in armada_37xx_get_func_reg()
225 if (!strcmp(grp->funcs[f], func)) in armada_37xx_get_func_reg()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-sabrelite.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
8 #include <dt-bindings/clock/imx6qdl-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
14 stdout-path = &uart2;
27 reg_2p5v: regulator-2p5v {
28 compatible = "regulator-fixed";
29 regulator-name = "2P5V";
30 regulator-min-microvolt = <2500000>;
31 regulator-max-microvolt = <2500000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/openbmc/linux/drivers/pinctrl/intel/
H A Dpinctrl-merrifield.c1 // SPDX-License-Identifier: GPL-2.0
18 #include "pinctrl-intel.h"
19 #include "pinctrl-tangier.h"
107 /* Family 6: GP SSP (22 pins) */
321 FUNCTION("pwm3", mrfld_pwm3_groups),
362 .name = "pinctrl-merrifield",
382 MODULE_ALIAS("platform:pinctrl-merrifield");
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-37xx.c6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
17 #include <linux/pinctrl/pinconf-generic.h>
28 #include "../pinctrl-utils.h"
176 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
232 *offset -= GPIO_PER_REG; in armada_37xx_update_reg()
240 while (*grp < info->ngroups) { in armada_37xx_find_next_grp_by_pin()
241 struct armada_37xx_pin_group *group = &info->groups[*grp]; in armada_37xx_find_next_grp_by_pin()
245 for (j = 0; j < (group->npins + group->extra_npins); j++) in armada_37xx_find_next_grp_by_pin()
246 if (group->pins[j] == pin) in armada_37xx_find_next_grp_by_pin()
255 return -ENOTSUPP; in armada_37xx_pin_config_group_get()
[all …]
/openbmc/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
302 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
309 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
354 #define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */
[all …]