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/openbmc/qemu/ui/
H A Dgtk-egl.c29 if (vc->gfx.scanout_mode == scanout) { in gtk_egl_set_scanout_mode()
33 vc->gfx.scanout_mode = scanout; in gtk_egl_set_scanout_mode()
34 if (!vc->gfx.scanout_mode) { in gtk_egl_set_scanout_mode()
35 eglMakeCurrent(qemu_egl_display, vc->gfx.esurface, in gtk_egl_set_scanout_mode()
36 vc->gfx.esurface, vc->gfx.ectx); in gtk_egl_set_scanout_mode()
37 egl_fb_destroy(&vc->gfx.guest_fb); in gtk_egl_set_scanout_mode()
38 if (vc->gfx.surface) { in gtk_egl_set_scanout_mode()
39 surface_gl_destroy_texture(vc->gfx.gls, vc->gfx.ds); in gtk_egl_set_scanout_mode()
40 surface_gl_create_texture(vc->gfx.gls, vc->gfx.ds); in gtk_egl_set_scanout_mode()
49 GdkWindow *gdk_window = gtk_widget_get_window(vc->gfx.drawing_area); in gd_egl_init()
[all …]
H A Dgtk-gl-area.c23 if (vc->gfx.scanout_mode == scanout) { in gtk_gl_area_set_scanout_mode()
27 vc->gfx.scanout_mode = scanout; in gtk_gl_area_set_scanout_mode()
28 if (!vc->gfx.scanout_mode) { in gtk_gl_area_set_scanout_mode()
29 gtk_gl_area_make_current(GTK_GL_AREA(vc->gfx.drawing_area)); in gtk_gl_area_set_scanout_mode()
30 egl_fb_destroy(&vc->gfx.guest_fb); in gtk_gl_area_set_scanout_mode()
31 if (vc->gfx.surface) { in gtk_gl_area_set_scanout_mode()
32 surface_gl_destroy_texture(vc->gfx.gls, vc->gfx.ds); in gtk_gl_area_set_scanout_mode()
33 surface_gl_create_texture(vc->gfx.gls, vc->gfx.ds); in gtk_gl_area_set_scanout_mode()
43 QemuDmaBuf *dmabuf = vc->gfx.guest_fb.dmabuf; in gd_gl_area_draw()
47 if (!vc->gfx.gls) { in gd_gl_area_draw()
[all …]
H A Dgtk.c198 !qemu_console_is_graphic(vc->gfx.dcl.con)) { in gd_update_cursor()
202 if (!gtk_widget_get_realized(vc->gfx.drawing_area)) { in gd_update_cursor()
206 window = gtk_widget_get_window(GTK_WIDGET(vc->gfx.drawing_area)); in gd_update_cursor()
207 if (s->full_screen || qemu_input_is_absolute(vc->gfx.dcl.con) || s->ptr_owner == vc) { in gd_update_cursor()
271 if (!vc->gfx.ds) { in gd_update_geometry_hints()
275 geo.min_width = surface_width(vc->gfx.ds) * VC_SCALE_MIN; in gd_update_geometry_hints()
276 geo.min_height = surface_height(vc->gfx.ds) * VC_SCALE_MIN; in gd_update_geometry_hints()
279 geo.min_width = surface_width(vc->gfx.ds) * vc->gfx.scale_x; in gd_update_geometry_hints()
280 geo.min_height = surface_height(vc->gfx.ds) * vc->gfx.scale_y; in gd_update_geometry_hints()
283 geo_widget = vc->gfx.drawing_area; in gd_update_geometry_hints()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_rlc.c40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
100 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
101 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
H A Damdgpu_gfx.c33 /* delay 0.1 second to enable gfx off feature */
39 * GPU GFX IP block helpers function.
47 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
48 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
49 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
58 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
59 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
60 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
61 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
62 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
[all …]
H A Dgfx_v6_0.c341 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v6_0_init_microcode()
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
349 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v6_0_init_microcode()
352 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
353 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
354 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
357 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v6_0_init_microcode()
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_init_microcode()
[all …]
H A Dgfx_v11_0.c42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
199 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
267 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
443 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
444 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
445 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
446 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
448 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
480 if ((adev->gfx.me_fw_version >= 1505) && in gfx_v11_0_check_fw_cp_gfx_shadow()
481 (adev->gfx.pfp_fw_version >= 1600) && in gfx_v11_0_check_fw_cp_gfx_shadow()
[all …]
H A Dgfx_v7_0.c889 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
890 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
891 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
892 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
938 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v7_0_init_microcode()
943 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v7_0_init_microcode()
948 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v7_0_init_microcode()
953 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v7_0_init_microcode()
[all …]
H A Dgfx_v8_0.c927 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_free_microcode()
929 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
930 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
931 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
934 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
986 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
989 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
993 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
[all …]
H A Dgfx_v9_0.c46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
893 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1083 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1084 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1085 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1086 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1087 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1088 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1090 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1095 adev->gfx.me_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
[all …]
H A Dgfx_v9_4_3.c34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; in gfx_v9_4_3_set_kiq_pm4_funcs()
196 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
343 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
347 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
354 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_4_3_free_microcode()
355 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_4_3_free_microcode()
356 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_4_3_free_microcode()
357 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_4_3_free_microcode()
[all …]
H A Damdgpu_atomfirmware.c791 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
792 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
793 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
794 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
795 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
796 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
797 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
798 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
799 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
801 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
[all …]
H A Damdgpu_kms.c226 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
227 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
230 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
231 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
234 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
235 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
238 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
239 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
242 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
243 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
[all …]
H A Dgfx_v10_0.c40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
3557 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx10_kiq_unmap_queues()
3625 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3880 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3881 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3882 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
3883 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
3884 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
3885 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
3887 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
[all …]
H A Damdgpu_ucode.c107 DRM_DEBUG("GFX\n"); in amdgpu_ucode_print_gfx_hdr()
125 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gfx_hdr()
687 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
688 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
689 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
690 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
691 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
692 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
693 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
694 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
[all …]
H A Damdgpu_gfx.h28 * GFX stuff
38 /* GFX current status */
165 * GFX configurations
223 /* gfx configure feature */
404 /* gfx status */
415 /* gfx off */
418 … gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: ad…
419 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
457 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
458 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((a…
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H A Damdgpu_amdkfd.c152 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
153 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
166 adev->gfx.mec_bitmap[0].queue_bitmap, in amdgpu_amdkfd_device_init()
173 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
174 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
390 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
393 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
396 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
399 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
402 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
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H A Damdgpu_debugfs.c130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
257 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_regs2_op()
433 if (adev->gfx.funcs->read_wave_data) in amdgpu_debugfs_gprwave_read()
434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
438 if (adev->gfx.funcs->read_wave_vgprs) in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
441 if (adev->gfx.funcs->read_wave_sgprs) in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
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H A Dimu_v11_0.c53 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, fw_name); in imu_v11_0_init_microcode()
56 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
57 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
58 //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version); in imu_v11_0_init_microcode()
63 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
68 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
78 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
90 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
93 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
96 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpu/
H A Daspeed-gfx.txt1 Device tree configuration for the GFX display device on the ASPEED SoCs
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
17 - resets: reset line that must be released to use the GFX device
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed-gfx.txt1 * Device tree bindings for Aspeed SoC Display Controller (GFX)
8 - compatible: "aspeed,ast2500-gfx", "syscon"
9 - reg: contains offset/length value of the GFX memory
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-i915-hwmon4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/directfb/directfb/
H A D0001-gfx-direct-Aboid-usng-VLAs-and-printf-formats.patch4 Subject: [PATCH] gfx,direct: Aboid usng VLAs and printf formats
17 src/gfx/util.cpp | 8 ++++----
33 diff --git a/src/gfx/util.cpp b/src/gfx/util.cpp
35 --- a/src/gfx/util.cpp
36 +++ b/src/gfx/util.cpp
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_1_ppsmc.h55 #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
56 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
61 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
67 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
71 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
72 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
83 #define PPSMC_MSG_RequestActiveWgp 0x27 ///< Request GFX active WGP number
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/fbida/files/
H A D0001-fbida-Include-missing-sys-types.h.patch7 ../git/gfx.h:43:5: error: unknown type name 'dev_t'; did you mean 'div_t'?
20 gfx.h | 1 +
23 --- a/gfx.h
24 +++ b/gfx.h

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