1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: USB2 ChipIdea USB controller 8 9maintainers: 10 - Xu Yang <xu.yang_2@nxp.com> 11 - Peng Fan <peng.fan@nxp.com> 12 13properties: 14 compatible: 15 oneOf: 16 - enum: 17 - chipidea,usb2 18 - lsi,zevio-usb 19 - nuvoton,npcm750-udc 20 - nvidia,tegra20-ehci 21 - nvidia,tegra20-udc 22 - nvidia,tegra30-ehci 23 - nvidia,tegra30-udc 24 - nvidia,tegra114-udc 25 - nvidia,tegra124-udc 26 - qcom,ci-hdrc 27 - items: 28 - enum: 29 - nvidia,tegra114-ehci 30 - nvidia,tegra124-ehci 31 - nvidia,tegra210-ehci 32 - const: nvidia,tegra30-ehci 33 - items: 34 - enum: 35 - fsl,imx23-usb 36 - fsl,imx25-usb 37 - fsl,imx28-usb 38 - fsl,imx35-usb 39 - fsl,imx50-usb 40 - fsl,imx51-usb 41 - fsl,imx53-usb 42 - fsl,imx6q-usb 43 - fsl,imx6sl-usb 44 - fsl,imx6sx-usb 45 - fsl,imx6ul-usb 46 - fsl,imx7d-usb 47 - fsl,vf610-usb 48 - const: fsl,imx27-usb 49 - items: 50 - enum: 51 - fsl,imx8dxl-usb 52 - fsl,imx8ulp-usb 53 - const: fsl,imx7ulp-usb 54 - const: fsl,imx6ul-usb 55 - items: 56 - enum: 57 - fsl,imx8mm-usb 58 - fsl,imx8mn-usb 59 - const: fsl,imx7d-usb 60 - const: fsl,imx27-usb 61 - items: 62 - enum: 63 - fsl,imx6sll-usb 64 - fsl,imx7ulp-usb 65 - const: fsl,imx6ul-usb 66 - const: fsl,imx27-usb 67 - items: 68 - const: xlnx,zynq-usb-2.20a 69 - const: chipidea,usb2 70 - items: 71 - enum: 72 - nuvoton,npcm845-udc 73 - const: nuvoton,npcm750-udc 74 75 reg: 76 minItems: 1 77 maxItems: 2 78 79 interrupts: 80 minItems: 1 81 maxItems: 2 82 83 clocks: 84 minItems: 1 85 maxItems: 3 86 87 clock-names: 88 minItems: 1 89 maxItems: 3 90 91 dr_mode: true 92 93 power-domains: 94 maxItems: 1 95 96 resets: 97 maxItems: 1 98 99 reset-names: 100 maxItems: 1 101 102 "#reset-cells": 103 const: 1 104 105 phy_type: true 106 107 itc-setting: 108 description: 109 interrupt threshold control register control, the setting should be 110 aligned with ITC bits at register USBCMD. 111 $ref: /schemas/types.yaml#/definitions/uint32 112 113 ahb-burst-config: 114 description: 115 it is vendor dependent, the required value should be aligned with 116 AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property is 117 used to change AHB burst configuration, check the chipidea spec for 118 meaning of each value. If this property is not existed, it will use 119 the reset value. 120 $ref: /schemas/types.yaml#/definitions/uint32 121 minimum: 0x0 122 maximum: 0x7 123 124 tx-burst-size-dword: 125 description: 126 it is vendor dependent, the tx burst size in dword (4 bytes), This 127 register represents the maximum length of a the burst in 32-bit 128 words while moving data from system memory to the USB bus, the value 129 of this property will only take effect if property "ahb-burst-config" 130 is set to 0, if this property is missing the reset default of the 131 hardware implementation will be used. 132 $ref: /schemas/types.yaml#/definitions/uint32 133 minimum: 0x0 134 maximum: 0x20 135 136 rx-burst-size-dword: 137 description: 138 it is vendor dependent, the rx burst size in dword (4 bytes), This 139 register represents the maximum length of a the burst in 32-bit words 140 while moving data from the USB bus to system memory, the value of 141 this property will only take effect if property "ahb-burst-config" 142 is set to 0, if this property is missing the reset default of the 143 hardware implementation will be used. 144 $ref: /schemas/types.yaml#/definitions/uint32 145 minimum: 0x0 146 maximum: 0x20 147 148 extcon: 149 description: 150 Phandles to external connector devices. First phandle should point 151 to external connector, which provide "USB" cable events, the second 152 should point to external connector device, which provide "USB-HOST" 153 cable events. If one of the external connector devices is not 154 required, empty <0> phandle should be specified. 155 $ref: /schemas/types.yaml#/definitions/phandle-array 156 minItems: 1 157 items: 158 - description: vbus extcon 159 - description: id extcon 160 161 phy-clkgate-delay-us: 162 description: 163 The delay time (us) between putting the PHY into low power mode and 164 gating the PHY clock. 165 166 non-zero-ttctrl-ttha: 167 description: 168 After setting this property, the value of register ttctrl.ttha 169 will be 0x7f; if not, the value will be 0x0, this is the default 170 value. It needs to be very carefully for setting this property, it 171 is recommended that consult with your IC engineer before setting 172 this value. On the most of chipidea platforms, the "usage_tt" flag 173 at RTL is 0, so this property only affects siTD. 174 175 If this property is not set, the max packet size is 1023 bytes, and 176 if the total of packet size for previous transactions are more than 177 256 bytes, it can't accept any transactions within this frame. The 178 use case is single transaction, but higher frame rate. 179 180 If this property is set, the max packet size is 188 bytes, it can 181 handle more transactions than above case, it can accept transactions 182 until it considers the left room size within frame is less than 188 183 bytes, software needs to make sure it does not send more than 90% 184 maximum_periodic_data_per_frame. The use case is multiple 185 transactions, but less frame rate. 186 type: boolean 187 188 mux-controls: 189 description: 190 The mux control for toggling host/device output of this controller. 191 It's expected that a mux state of 0 indicates device mode and a mux 192 state of 1 indicates host mode. 193 maxItems: 1 194 195 mux-control-names: 196 const: usb_switch 197 198 operating-points-v2: 199 description: A phandle to the OPP table containing the performance states. 200 $ref: /schemas/types.yaml#/definitions/phandle 201 202 pinctrl-names: 203 description: 204 Names for optional pin modes in "default", "host", "device". 205 In case of HSIC-mode, "idle" and "active" pin modes are mandatory. 206 In this case, the "idle" state needs to pull down the data and 207 strobe pin and the "active" state needs to pull up the strobe pin. 208 oneOf: 209 - items: 210 - const: idle 211 - const: active 212 - items: 213 - const: default 214 - enum: 215 - host 216 - device 217 - items: 218 - const: default 219 220 pinctrl-0: 221 maxItems: 1 222 223 pinctrl-1: 224 maxItems: 1 225 226 phys: 227 maxItems: 1 228 229 phy-names: 230 const: usb-phy 231 232 phy-select: 233 description: 234 Phandler of TCSR node with two argument that indicate register 235 offset, and phy index 236 $ref: /schemas/types.yaml#/definitions/phandle-array 237 items: 238 - description: phandle to TCSR node 239 - description: register offset 240 - description: phy index 241 242 vbus-supply: 243 description: reference to the VBUS regulator. 244 245 fsl,usbmisc: 246 description: 247 Phandler of non-core register device, with one argument that 248 indicate usb controller index 249 $ref: /schemas/types.yaml#/definitions/phandle-array 250 items: 251 - items: 252 - description: phandle to usbmisc node 253 - description: index of usb controller 254 255 fsl,anatop: 256 description: phandle for the anatop node. 257 $ref: /schemas/types.yaml#/definitions/phandle 258 259 disable-over-current: 260 type: boolean 261 description: disable over current detect 262 263 over-current-active-low: 264 type: boolean 265 description: over current signal polarity is active low 266 267 over-current-active-high: 268 type: boolean 269 description: 270 Over current signal polarity is active high. It's recommended to 271 specify the over current polarity. 272 273 power-active-high: 274 type: boolean 275 description: power signal polarity is active high 276 277 external-vbus-divider: 278 type: boolean 279 description: enables off-chip resistor divider for Vbus 280 281 samsung,picophy-pre-emp-curr-control: 282 description: 283 HS Transmitter Pre-Emphasis Current Control. This signal controls 284 the amount of current sourced to the USB_OTG*_DP and USB_OTG*_DN 285 pins after a J-to-K or K-to-J transition. The range is from 0x0 to 286 0x3, the default value is 0x1. Details can refer to TXPREEMPAMPTUNE0 287 bits of USBNC_n_PHY_CFG1. 288 $ref: /schemas/types.yaml#/definitions/uint32 289 minimum: 0x0 290 maximum: 0x3 291 292 samsung,picophy-dc-vol-level-adjust: 293 description: 294 HS DC Voltage Level Adjustment. Adjust the high-speed transmitter DC 295 level voltage. The range is from 0x0 to 0xf, the default value is 296 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. 297 $ref: /schemas/types.yaml#/definitions/uint32 298 minimum: 0x0 299 maximum: 0xf 300 301 fsl,picophy-rise-fall-time-adjust: 302 description: 303 HS Transmitter Rise/Fall Time Adjustment. Adjust the rise/fall times 304 of the high-speed transmitter waveform. It has no unit. The rise/fall 305 time will be increased or decreased by a certain percentage relative 306 to design default time. (0:-10%; 1:design default; 2:+15%; 3:+20%) 307 Details can refer to TXRISETUNE0 bit of USBNC_n_PHY_CFG1. 308 $ref: /schemas/types.yaml#/definitions/uint32 309 minimum: 0 310 maximum: 3 311 default: 1 312 313 usb-phy: 314 description: phandle for the PHY device. Use "phys" instead. 315 $ref: /schemas/types.yaml#/definitions/phandle 316 deprecated: true 317 318 fsl,usbphy: 319 description: phandle of usb phy that connects to the port. Use "phys" instead. 320 $ref: /schemas/types.yaml#/definitions/phandle 321 deprecated: true 322 323 nvidia,phy: 324 description: phandle of usb phy that connects to the port. Use "phys" instead. 325 $ref: /schemas/types.yaml#/definitions/phandle 326 deprecated: true 327 328 nvidia,needs-double-reset: 329 description: Indicates double reset or not. 330 type: boolean 331 deprecated: true 332 333 port: 334 description: 335 Any connector to the data bus of this controller should be modelled 336 using the OF graph bindings specified, if the "usb-role-switch" 337 property is used. 338 $ref: /schemas/graph.yaml#/properties/port 339 340 reset-gpios: 341 maxItems: 1 342 343 ulpi: 344 type: object 345 additionalProperties: false 346 patternProperties: 347 "^phy(-[0-9])?$": 348 description: The phy child node for Qcom chips. 349 type: object 350 $ref: /schemas/phy/qcom,usb-hs-phy.yaml 351 352dependencies: 353 port: [ usb-role-switch ] 354 mux-controls: [ mux-control-names ] 355 356required: 357 - compatible 358 - reg 359 - interrupts 360 361allOf: 362 - $ref: usb-hcd.yaml# 363 - $ref: usb-drd.yaml# 364 - if: 365 properties: 366 phy_type: 367 const: hsic 368 required: 369 - phy_type 370 then: 371 properties: 372 pinctrl-names: 373 items: 374 - const: idle 375 - const: active 376 else: 377 properties: 378 pinctrl-names: 379 minItems: 1 380 maxItems: 2 381 oneOf: 382 - items: 383 - const: default 384 - enum: 385 - host 386 - device 387 - items: 388 - const: default 389 - if: 390 properties: 391 compatible: 392 contains: 393 enum: 394 - chipidea,usb2 395 - lsi,zevio-usb 396 - nuvoton,npcm750-udc 397 - nvidia,tegra20-udc 398 - nvidia,tegra30-udc 399 - nvidia,tegra114-udc 400 - nvidia,tegra124-udc 401 - qcom,ci-hdrc 402 - xlnx,zynq-usb-2.20a 403 then: 404 properties: 405 fsl,usbmisc: false 406 disable-over-current: false 407 over-current-active-low: false 408 over-current-active-high: false 409 power-active-high: false 410 external-vbus-divider: false 411 samsung,picophy-pre-emp-curr-control: false 412 samsung,picophy-dc-vol-level-adjust: false 413 414unevaluatedProperties: false 415 416examples: 417 - | 418 #include <dt-bindings/interrupt-controller/arm-gic.h> 419 #include <dt-bindings/clock/berlin2.h> 420 421 usb@f7ed0000 { 422 compatible = "chipidea,usb2"; 423 reg = <0xf7ed0000 0x10000>; 424 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&chip CLKID_USB0>; 426 phys = <&usb_phy0>; 427 phy-names = "usb-phy"; 428 vbus-supply = <®_usb0_vbus>; 429 itc-setting = <0x4>; /* 4 micro-frames */ 430 /* Incremental burst of unspecified length */ 431 ahb-burst-config = <0x0>; 432 tx-burst-size-dword = <0x10>; /* 64 bytes */ 433 rx-burst-size-dword = <0x10>; 434 extcon = <0>, <&usb_id>; 435 phy-clkgate-delay-us = <400>; 436 mux-controls = <&usb_switch>; 437 mux-control-names = "usb_switch"; 438 }; 439 440 # Example for HSIC: 441 - | 442 #include <dt-bindings/interrupt-controller/arm-gic.h> 443 #include <dt-bindings/clock/imx6qdl-clock.h> 444 445 usb@2184400 { 446 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 447 reg = <0x02184400 0x200>; 448 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clks IMX6QDL_CLK_USBOH3>; 450 fsl,usbphy = <&usbphynop1>; 451 fsl,usbmisc = <&usbmisc 2>; 452 phy_type = "hsic"; 453 dr_mode = "host"; 454 ahb-burst-config = <0x0>; 455 tx-burst-size-dword = <0x10>; 456 rx-burst-size-dword = <0x10>; 457 pinctrl-names = "idle", "active"; 458 pinctrl-0 = <&pinctrl_usbh2_idle>; 459 pinctrl-1 = <&pinctrl_usbh2_active>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 463 ethernet@1 { 464 compatible = "usb424,9730"; 465 reg = <1>; 466 }; 467 }; 468 469... 470