Searched +full:exynos +full:- +full:sysmmu (Results 1 – 18 of 18) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.014 #include <dt-bindings/clock/exynos5420.h>15 #include <dt-bindings/clock/exynos-audss-clk.h>16 #include <dt-bindings/interrupt-controller/arm-gic.h>37 bus_disp1: bus-disp1 {38 compatible = "samsung,exynos-bus";40 clock-names = "bus";44 bus_disp1_fimd: bus-disp1-fimd {45 compatible = "samsung,exynos-bus";47 clock-names = "bus";[all …]
1 // SPDX-License-Identifier: GPL-2.017 #include <dt-bindings/clock/exynos5250.h>19 #include "exynos4-cpu-thermal.dtsi"20 #include <dt-bindings/clock/exynos-audss-clk.h>46 #address-cells = <1>;47 #size-cells = <0>;49 cpu-map {62 compatible = "arm,cortex-a15";65 clock-names = "cpu";66 operating-points-v2 = <&cpu0_opp_table>;[all …]
1 // SPDX-License-Identifier: GPL-2.019 #include "exynos4-cpu-thermal.dtsi"27 fimc-lite0 = &fimc_lite_0;28 fimc-lite1 = &fimc_lite_1;31 bus_acp: bus-acp {32 compatible = "samsung,exynos-bus";34 clock-names = "bus";35 operating-points-v2 = <&bus_acp_opp_table>;38 bus_acp_opp_table: opp-table {39 compatible = "operating-points-v2";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.7 * Copyright (c) 2010-2011 Linaro Ltd.19 #include <dt-bindings/clock/exynos4.h>20 #include <dt-bindings/clock/exynos-audss-clk.h>21 #include <dt-bindings/interrupt-controller/arm-gic.h>22 #include <dt-bindings/interrupt-controller/irq.h>25 interrupt-parent = <&gic>;26 #address-cells = <1>;27 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.7 * Copyright (c) 2010-2011 Linaro Ltd.20 #include "exynos4-cpu-thermal.dtsi"31 bus_acp: bus-acp {32 compatible = "samsung,exynos-bus";34 clock-names = "bus";35 operating-points-v2 = <&bus_acp_opp_table>;38 bus_acp_opp_table: opp-table {39 compatible = "operating-points-v2";[all …]
1 // SPDX-License-Identifier: GPL-2.017 #include "exynos4-cpu-thermal.dtsi"18 #include <dt-bindings/clock/exynos3250.h>19 #include <dt-bindings/interrupt-controller/arm-gic.h>20 #include <dt-bindings/interrupt-controller/irq.h>24 interrupt-parent = <&gic>;25 #address-cells = <1>;26 #size-cells = <1>;46 bus_dmc: bus-dmc {47 compatible = "samsung,exynos-bus";[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)10 - Marek Szyprowski <m.szyprowski@samsung.com>13 Samsung's Exynos architecture contains System MMUs that enables scattered14 physical memory chunks visible as a contiguous region to DMA-capable peripheral15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.20 another capabilities like L2 TLB or block-fetch buffers to minimize translation[all …]
1 Exynos Display Controller5 compatible: should be "samsung,exynos-fimd"9 samsung,vl-col: X resolution of the panel10 samsung,vl-row: Y resolution of the panel11 samsung,vl-freq: Refresh rate12 samsung,vl-bpix: Bits per pixel13 samsung,vl-hspw: Hsync value14 samsung,vl-hfpd: Right margin15 samsung,vl-hbpd: Left margin16 samsung,vl-vspw: Vsync value[all …]
1 // SPDX-License-Identifier: GPL-2.013 #include <dt-bindings/clock/exynos850.h>14 #include <dt-bindings/interrupt-controller/arm-gic.h>15 #include <dt-bindings/soc/samsung,exynos-usi.h>20 #address-cells = <2>;21 #size-cells = <1>;23 interrupt-parent = <&gic>;34 arm-pmu {35 compatible = "arm,cortex-a55-pmu";44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,[all …]
1 // SPDX-License-Identifier: GPL-2.016 #include <dt-bindings/clock/exynos5433.h>17 #include <dt-bindings/interrupt-controller/arm-gic.h>21 #address-cells = <2>;22 #size-cells = <2>;24 interrupt-parent = <&gic>;26 arm-a53-pmu {27 compatible = "arm,cortex-a53-pmu";32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;35 arm-a57-pmu {[all …]
1 // SPDX-License-Identifier: GPL-2.0-only12 #include <linux/dma-mapping.h>37 #define SECT_MASK (~(SECT_SIZE - 1))38 #define LPAGE_MASK (~(LPAGE_SIZE - 1))39 #define SPAGE_MASK (~(SPAGE_SIZE - 1))54 * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces57 * All SYSMMU controllers in the system support the address spaces of the same58 * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper61 static short PG_ENT_SHIFT = -1;97 #define section_offs(iova) (iova & (SECT_SIZE - 1))[all …]
1 // SPDX-License-Identifier: GPL-2.0+8 #include "exynos54xx-pinctrl.dtsi"12 machine-arch-id = <4151>;45 compatible = "samsung,exynos-adc-v2";52 #address-cells = <1>;53 #size-cells = <0>;54 compatible = "samsung,exynos5-hsi2c";60 #address-cells = <1>;61 #size-cells = <0>;62 compatible = "samsung,exynos5-hsi2c";[all …]
1 // SPDX-License-Identifier: GPL-2.0+104 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_dualrgb()112 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()116 writel(cfg, ®->dualrgb); in exynos_fimd_set_dualrgb()122 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_dp_clkcon()128 writel(cfg, ®->dp_mie_clkcon); in exynos_fimd_set_dp_clkcon()134 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_par()138 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_set_par()154 switch (priv->vl_bpix) { in exynos_fimd_set_par()163 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_set_par()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */12 * drivers and board-specific code within U-Boot. It aims to reduce the13 * amount of FDT munging required within U-Boot itself, so that driver code27 #define FDT_ADDR_T_NONE (-1U)32 #define FDT_ADDR_T_NONE (-1U)59 * be equal to: end - start + 1.93 * t: is 1 if the address is aliased (for non-relocatable I/O) below 1MB96 * bbbbbbbb: is the 8-bit Bus Number97 * ddddd: is the 5-bit Device Number98 * fff: is the 3-bit Function Number[all …]
1 // SPDX-License-Identifier: GPL-2.0+30 * good reason why driver-model conversion is infeasible. Examples include36 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),37 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),38 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),39 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),40 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),42 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),43 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),44 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),[all …]
... --------------------- ...
5 ----------[all...]
1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa[all...]