Searched +full:event +full:- +full:to +full:- +full:mhpmevent (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: BSD-2-Clause3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V SBI PMU events10 - Atish Patra <atishp@rivosinc.com>13 The SBI PMU extension allows supervisor software to configure, start and18 The platform must provide information about PMU event to counter mappings19 either via device tree or another way, specific to the platform.20 Without the event to counter mappings, the SBI PMU extension cannot be used.22 Platforms should provide information about the PMU event selector values[all …]
2 * RISC-V PMU file.21 #include "qemu/error-report.h"25 #include "sysemu/cpu-timers.h"31 * To keep it simple, any event can be mapped to any programmable counters in34 * to provide the correct value as well. Heterogeneous PMU per hart is not42 * The event encoding is specified in the SBI specification in riscv_pmu_generate_fdt_node()43 * Event idx is a 20bits wide number encoded as follows: in riscv_pmu_generate_fdt_node()78 qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", in riscv_pmu_generate_fdt_node()85 !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { in riscv_pmu_counter_valid()94 CPURISCVState *env = &cpu->env; in riscv_pmu_counter_enabled()[all …]