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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sdx55-pcie-ep
17 - qcom,sm8450-pcie-ep
18 - items:
19 - const: qcom,sdx65-pcie-ep
[all …]
H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
[all …]
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
[all …]
H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dwarp.dts4 * Copyright (c) 2008-2009 PIKA Technologies
12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 model = "PowerPC,440EP";
34 clock-frequency = <0>; /* Filled in by zImage */
35 timebase-frequency = <0>; /* Filled in by zImage */
[all …]
H A Dhotfoot.dts4 * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 model = "PowerPC,405EP";
35 clock-frequency = <0>; /* Filled in by zImage */
36 timebase-frequency = <0>; /* Filled in by zImage */
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx55-telit-fn980-tlb.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-telit-fn980-tlb", "qcom,sdx55";
16 qcom,board-id = <0xb010008 0x0>;
23 stdout-path = "serial0:921600n8";
26 reserved-memory {
27 #address-cells = <1>;
[all …]
H A Dqcom-sdx65-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 /dts-v1/;
7 #include "qcom-sdx65.dtsi"
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
15 compatible = "qcom,sdx65-mtp", "qcom,sdx65";
16 qcom,board-id = <0x2010008 0x302>;
23 stdout-path = "serial0:115200n8";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Datomisp_csi2_bridge.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on drivers/media/pci/intel/ipu3/cio2-bridge.c written by:
18 #include <media/ipu-bridge.h>
19 #include <media/v4l2-fwnode.h>
28 * 79234640-9e10-4fea-a5c1-b5aa8b19756f
52 * 822ace8f-2814-4174-a56b-5f029fe079ee
61 * dc2f6c4f-045b-4f1d-97b9-882a6860a4be
70 * 75c9a639-5c8a-4a00-9f48-a9c3b5da789f
94 * Once all sensors are moved to v4l2-async probing atomisp_gmin_platform.c can
114 DMI_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10"),
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-rock960.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-rock960.dtsi"
14 stdout-path = "serial2:1500000n8";
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>,
24 user_led1: led-1 {
26 gpios = <&gpio4 RK_PC2 0>;
27 linux,default-trigger = "heartbeat";
[all …]
H A Drk3399-ficus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
10 #include "rk3399-rock960.dtsi"
17 stdout-path = "serial2:1500000n8";
20 clkin_gmac: external-gmac-clock {
21 compatible = "fixed-clock";
22 clock-frequency = <125000000>;
23 clock-output-names = "clkin_gmac";
24 #clock-cells = <0>;
28 compatible = "gpio-leds";
[all …]
H A Drk3399-khadas-edge-captain.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "rk3399-khadas-edge.dtsi"
11 model = "Khadas Edge-Captain";
12 compatible = "khadas,edge-captain", "rockchip,rk3399";
24 ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
25 num-lanes = <4>;
H A Drk3399-khadas-edge-v.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "rk3399-khadas-edge.dtsi"
11 model = "Khadas Edge-V";
12 compatible = "khadas,edge-v", "rockchip,rk3399";
24 ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
25 num-lanes = <4>;
H A Drk3399pro.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
17 ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
18 num-lanes = <4>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pcie_clkreqn_cpm>;
H A Drk3399-nanopc-t4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-T4 board device tree source
11 /dts-v1/;
12 #include "rk3399-nanopi4.dtsi"
15 model = "FriendlyElec NanoPC-T4";
16 compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
18 vcc12v0_sys: vcc12v0-sys {
19 compatible = "regulator-fixed";
20 regulator-always-on;
21 regulator-boot-on;
[all …]
H A Drk3399-sapphire-excavator.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-sapphire.dtsi"
10 model = "Excavator-RK3399 Board";
11 compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
17 adc-keys {
18 compatible = "adc-keys";
19 io-channels = <&saradc 1>;
20 io-channel-names = "buttons";
21 keyup-threshold-microvolt = <1800000>;
[all …]
H A Drk3399-puma-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-puma.dtsi"
10 model = "Theobroma Systems RK3399-Q7 SoM";
11 compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
18 stdout-path = "serial0:115200n8";
22 pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
24 sd_card_led: led-1 {
26 gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
27 linux,default-trigger = "mmc0";
[all …]
H A Drk3399-roc-pc-mezzanine.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
7 /dts-v1/;
8 #include "rk3399-roc-pc.dtsi"
11 model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
19 poe_12v: poe-12v {
20 compatible = "regulator-fixed";
21 regulator-name = "poe_12v";
22 regulator-always-on;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-rock960.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include "rk3399-rock960.dtsi"
8 #include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
15 stdout-path = "serial2:1500000n8";
20 ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
25 pcie_drv: pcie-drv {
32 host_vbus_drv: host-vbus-drv {
H A Drk3399-ficus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
10 #include "rk3399-rock960.dtsi"
11 #include "rk3399-sdram-ddr3-1600.dtsi"
18 stdout-path = "serial2:1500000n8";
21 clkin_gmac: external-gmac-clock {
22 compatible = "fixed-clock";
23 clock-frequency = <125000000>;
24 clock-output-names = "clkin_gmac";
25 #clock-cells = <0>;
[all …]
H A Dat91sam9rl.dtsi2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
19 interrupt-parent = <&aic>;
42 compatible = "arm,arm926ej-s";
53 compatible = "fixed-clock";
[all …]
H A Dat91sam9x5.dtsi2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
13 #include <dt-bindings/dma/at91.h>
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
22 interrupt-parent = <&aic>;
45 compatible = "arm,arm926ej-s";
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
[all …]
/openbmc/u-boot/drivers/usb/gadget/
H A Dat91_udc.c1 // SPDX-License-Identifier: GPL-2.0+
6 * at91_udc -- driver for at91-series USB peripheral controller
31 * This controller is simple and PIO-only. It's used in many AT91-series
33 * at91sam926x (arm926ejs, with MMU), and several no-mmu versions.
35 * This driver expects the board has been wired with two GPIOs supporting
55 "ep3-int",
62 __raw_readl((udc)->udp_baseaddr + (reg))
64 __raw_writel((val), (udc)->udp_baseaddr + (reg))
68 /*-------------------------------------------------------------------------*/
70 static void done(struct at91_ep *ep, struct at91_request *req, int status) in done() argument
[all …]
/openbmc/linux/drivers/usb/gadget/udc/
H A Dat91_udc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * at91_udc -- driver for at91-series USB peripheral controller
32 #include <linux/mfd/syscon/atmel-matrix.h>
38 * This controller is simple and PIO-only. It's used in many AT91-series
40 * at91sam926x (arm926ejs, with MMU), and several no-mmu versions.
42 * This driver expects the board has been wired with two GPIOs supporting
75 EP_INFO("ep3-int",
90 __raw_readl((udc)->udp_baseaddr + (reg))
92 __raw_writel((val), (udc)->udp_baseaddr + (reg))
94 /*-------------------------------------------------------------------------*/
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]

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