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/openbmc/qemu/target/i386/
H A Dhelper.h5 DEF_HELPER_3(write_eflags, void, env, tl, i32)
6 DEF_HELPER_1(read_eflags, tl, env)
7 DEF_HELPER_2(divb_AL, void, env, tl)
8 DEF_HELPER_2(idivb_AL, void, env, tl)
9 DEF_HELPER_2(divw_AX, void, env, tl)
10 DEF_HELPER_2(idivw_AX, void, env, tl)
11 DEF_HELPER_2(divl_EAX, void, env, tl)
12 DEF_HELPER_2(idivl_EAX, void, env, tl)
14 DEF_HELPER_2(divq_EAX, void, env, tl)
15 DEF_HELPER_2(idivq_EAX, void, env, tl)
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dsystem_helper.h.inc13 DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
14 DEF_HELPER_1(mfc0_mvpconf0, tl, env)
15 DEF_HELPER_1(mfc0_mvpconf1, tl, env)
16 DEF_HELPER_1(mftc0_vpecontrol, tl, env)
17 DEF_HELPER_1(mftc0_vpeconf0, tl, env)
18 DEF_HELPER_1(mfc0_random, tl, env)
19 DEF_HELPER_1(mfc0_tcstatus, tl, env)
20 DEF_HELPER_1(mftc0_tcstatus, tl, env)
21 DEF_HELPER_1(mfc0_tcbind, tl, env)
22 DEF_HELPER_1(mftc0_tcbind, tl, env)
[all …]
H A Dmsa_helper.h.inc13 DEF_HELPER_3(msa_nloc_b, void, env, i32, i32)
14 DEF_HELPER_3(msa_nloc_h, void, env, i32, i32)
15 DEF_HELPER_3(msa_nloc_w, void, env, i32, i32)
16 DEF_HELPER_3(msa_nloc_d, void, env, i32, i32)
18 DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32)
19 DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)
20 DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)
21 DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)
23 DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32)
24 DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)
[all …]
H A Dfpu_helper.c40 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) in helper_cfc1() argument
46 arg1 = (int32_t)env->active_fpu.fcr0; in helper_cfc1()
50 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) { in helper_cfc1()
51 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_cfc1()
53 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR); in helper_cfc1()
55 do_raise_exception(env, EXCP_RI, GETPC()); in helper_cfc1()
61 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { in helper_cfc1()
62 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_cfc1()
63 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1; in helper_cfc1()
65 helper_raise_exception(env, EXCP_RI); in helper_cfc1()
[all …]
/openbmc/qemu/target/riscv/
H A Dfpu_helper.c27 target_ulong riscv_cpu_get_fflags(CPURISCVState *env) in riscv_cpu_get_fflags() argument
29 int soft = get_float_exception_flags(&env->fp_status); in riscv_cpu_get_fflags()
41 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) in riscv_cpu_set_fflags() argument
51 set_float_exception_flags(soft, &env->fp_status); in riscv_cpu_set_fflags()
54 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode() argument
59 rm = env->frm; in helper_set_rounding_mode()
78 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); in helper_set_rounding_mode()
81 set_float_rounding_mode(softrm, &env->fp_status); in helper_set_rounding_mode()
84 void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode_chkfrm() argument
89 if (unlikely(env->frm >= 5)) { in helper_set_rounding_mode_chkfrm()
[all …]
H A Dhelper.h2 DEF_HELPER_2(raise_exception, noreturn, env, i32)
5 DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
6 DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32)
9 DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
10 DEF_HELPER_FLAGS_4(fmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
11 DEF_HELPER_FLAGS_4(fmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
12 DEF_HELPER_FLAGS_4(fmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
13 DEF_HELPER_FLAGS_4(fmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
14 DEF_HELPER_FLAGS_4(fmsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
15 DEF_HELPER_FLAGS_4(fnmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
[all …]
H A Dop_helper.c31 G_NORETURN void riscv_raise_exception(CPURISCVState *env, in riscv_raise_exception() argument
35 CPUState *cs = env_cpu(env); in riscv_raise_exception()
39 env->pc); in riscv_raise_exception()
45 void helper_raise_exception(CPURISCVState *env, uint32_t exception) in helper_raise_exception() argument
47 riscv_raise_exception(env, exception, 0); in helper_raise_exception()
50 target_ulong helper_csrr(CPURISCVState *env, int csr) in helper_csrr() argument
58 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); in helper_csrr()
62 RISCVException ret = riscv_csrr(env, csr, &val); in helper_csrr()
65 riscv_raise_exception(env, ret, GETPC()); in helper_csrr()
70 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) in helper_csrw() argument
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dhelper-mve.h19 DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32)
20 DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32)
21 DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32)
22 DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32)
23 DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32)
24 DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32)
26 DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32)
27 DEF_HELPER_FLAGS_3(mve_vldrb_sw, TCG_CALL_NO_WG, void, env, ptr, i32)
28 DEF_HELPER_FLAGS_3(mve_vldrb_uh, TCG_CALL_NO_WG, void, env, ptr, i32)
29 DEF_HELPER_FLAGS_3(mve_vldrb_uw, TCG_CALL_NO_WG, void, env, ptr, i32)
[all …]
/openbmc/qemu/target/sparc/
H A Dwin_helper.c27 void cpu_set_cwp(CPUSPARCState *env, int new_cwp) in cpu_set_cwp() argument
30 if (env->cwp == env->nwindows - 1) { in cpu_set_cwp()
31 memcpy(env->regbase, env->regbase + env->nwindows * 16, in cpu_set_cwp()
32 sizeof(env->gregs)); in cpu_set_cwp()
34 env->cwp = new_cwp; in cpu_set_cwp()
37 if (new_cwp == env->nwindows - 1) { in cpu_set_cwp()
38 memcpy(env->regbase + env->nwindows * 16, env->regbase, in cpu_set_cwp()
39 sizeof(env->gregs)); in cpu_set_cwp()
41 env->regwptr = env->regbase + (new_cwp * 16); in cpu_set_cwp()
44 target_ulong cpu_get_psr(CPUSPARCState *env) in cpu_get_psr() argument
[all …]
H A Dfop_helper.c48 static void check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) in check_ieee_exceptions() argument
50 target_ulong status = get_float_exception_flags(&env->fp_status); in check_ieee_exceptions()
55 set_float_exception_flags(0, &env->fp_status); in check_ieee_exceptions()
74 if (cexc & (env->fsr >> FSR_TEM_SHIFT)) { in check_ieee_exceptions()
76 env->fsr_cexc_ftt = cexc | FSR_FTT_IEEE_EXCP; in check_ieee_exceptions()
77 cpu_raise_exception_ra(env, TT_FP_EXCP, ra); in check_ieee_exceptions()
81 env->fsr |= cexc << FSR_AEXC_SHIFT; in check_ieee_exceptions()
85 env->fsr_cexc_ftt = cexc; in check_ieee_exceptions()
88 float32 helper_fadds(CPUSPARCState *env, float32 src1, float32 src2) in helper_fadds() argument
90 float32 ret = float32_add(src1, src2, &env->fp_status); in helper_fadds()
[all …]
/openbmc/qemu/linux-user/xtensa/
H A Dcpu_loop.c26 static void xtensa_rfw(CPUXtensaState *env) in xtensa_rfw() argument
28 xtensa_restore_owb(env); in xtensa_rfw()
29 env->pc = env->sregs[EPC1]; in xtensa_rfw()
32 static void xtensa_rfwu(CPUXtensaState *env) in xtensa_rfwu() argument
34 env->sregs[WINDOW_START] |= (1 << env->sregs[WINDOW_BASE]); in xtensa_rfwu()
35 xtensa_rfw(env); in xtensa_rfwu()
38 static void xtensa_rfwo(CPUXtensaState *env) in xtensa_rfwo() argument
40 env->sregs[WINDOW_START] &= ~(1 << env->sregs[WINDOW_BASE]); in xtensa_rfwo()
41 xtensa_rfw(env); in xtensa_rfwo()
44 static void xtensa_overflow4(CPUXtensaState *env) in xtensa_overflow4() argument
[all …]
/openbmc/qemu/target/ppc/
H A Dhelper.h1 DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, noreturn, env, i32, i32)
2 DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
3 DEF_HELPER_FLAGS_4(TW, TCG_CALL_NO_WG, void, env, tl, tl, i32)
5 DEF_HELPER_FLAGS_4(TD, TCG_CALL_NO_WG, void, env, tl, tl, i32)
7 DEF_HELPER_4(HASHST, void, env, tl, tl, tl)
8 DEF_HELPER_4(HASHCHK, void, env, tl, tl, tl)
9 DEF_HELPER_4(HASHSTP, void, env, tl, tl, tl)
10 DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl)
12 DEF_HELPER_2(store_msr, void, env, tl)
13 DEF_HELPER_1(ppc_maybe_interrupt, void, env)
[all …]
/openbmc/qemu/target/i386/tcg/system/
H A Dsvm_helper.c30 static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr, in svm_save_seg() argument
33 cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), in svm_save_seg()
35 cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), in svm_save_seg()
37 cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), in svm_save_seg()
39 cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), in svm_save_seg()
49 static inline void svm_canonicalization(CPUX86State *env, target_ulong *seg_base) in svm_canonicalization() argument
51 uint16_t shift_amt = 64 - cpu_x86_virtual_addr_width(env); in svm_canonicalization()
55 static void svm_load_seg(CPUX86State *env, int mmu_idx, hwaddr addr, in svm_load_seg() argument
61 cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), in svm_load_seg()
64 cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), in svm_load_seg()
[all …]
/openbmc/qemu/target/mips/tcg/system/
H A Dcp0_helper.c37 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local
43 return cpu->halted && mips_vpe_active(env); in mips_vpe_is_wfi()
49 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local
51 return cpu->halted && mips_vp_active(env); in mips_vp_is_wfi()
80 CPUMIPSState *c = &cpu->env; in mips_tc_wake()
90 CPUMIPSState *c = &cpu->env; in mips_tc_sleep()
100 * @env: CPU from which mapping is performed.
112 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) in mips_cpu_map_tc() argument
120 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { in mips_cpu_map_tc()
122 *tc = env->current_tc; in mips_cpu_map_tc()
[all …]
H A Dtlb_helper.c32 static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) in r4k_mips_tlb_flush_extra() argument
34 /* Discard entries from env->tlb[first] onwards. */ in r4k_mips_tlb_flush_extra()
35 while (env->tlb->tlb_in_use > first) { in r4k_mips_tlb_flush_extra()
36 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); in r4k_mips_tlb_flush_extra()
50 static void r4k_fill_tlb(CPUMIPSState *env, int idx) in r4k_fill_tlb() argument
53 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); in r4k_fill_tlb()
56 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_fill_tlb()
57 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { in r4k_fill_tlb()
62 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); in r4k_fill_tlb()
64 tlb->VPN &= env->SEGMask; in r4k_fill_tlb()
[all …]
/openbmc/qemu/target/loongarch/tcg/
H A Dfpu_helper.c29 void restore_fp_status(CPULoongArchState *env) in restore_fp_status() argument
31 set_float_rounding_mode(ieee_rm[(env->fcsr0 >> FCSR0_RM) & 0x3], in restore_fp_status()
32 &env->fp_status); in restore_fp_status()
33 set_flush_to_zero(0, &env->fp_status); in restore_fp_status()
34 set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); in restore_fp_status()
39 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); in restore_fp_status()
40 set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); in restore_fp_status()
42 set_float_default_nan_pattern(0b01000000, &env->fp_status); in restore_fp_status()
66 static void update_fcsr0_mask(CPULoongArchState *env, uintptr_t pc, int mask) in update_fcsr0_mask() argument
68 int flags = get_float_exception_flags(&env->fp_status); in update_fcsr0_mask()
[all …]
/openbmc/qemu/target/m68k/
H A Dhelper.h4 DEF_HELPER_4(divuw, void, env, int, i32, int)
5 DEF_HELPER_4(divsw, void, env, int, s32, int)
6 DEF_HELPER_5(divul, void, env, int, int, i32, int)
7 DEF_HELPER_5(divsl, void, env, int, int, s32, int)
8 DEF_HELPER_5(divull, void, env, int, int, i32, int)
9 DEF_HELPER_5(divsll, void, env, int, int, s32, int)
10 DEF_HELPER_2(set_sr, void, env, i32)
11 DEF_HELPER_3(cf_movec_to, void, env, i32, i32)
12 DEF_HELPER_3(m68k_movec_to, void, env, i32, i32)
13 DEF_HELPER_2(m68k_movec_from, i32, env, i32)
[all …]
/openbmc/qemu/target/rx/
H A Dop_helper.c29 void raise_exception(CPURXState *env, int index,
32 static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte) in _set_psw() argument
35 prev_u = env->psw_u; in _set_psw()
36 rx_cpu_unpack_psw(env, psw, rte); in _set_psw()
37 if (prev_u != env->psw_u) { in _set_psw()
39 if (env->psw_u) { in _set_psw()
40 env->isp = env->regs[0]; in _set_psw()
41 env->regs[0] = env->usp; in _set_psw()
43 env->usp = env->regs[0]; in _set_psw()
44 env->regs[0] = env->isp; in _set_psw()
[all …]
/openbmc/qemu/target/sh4/
H A Dop_helper.c49 void helper_ldtlb(CPUSH4State *env) in helper_ldtlb() argument
52 cpu_abort(env_cpu(env), "Unhandled ldtlb"); in helper_ldtlb()
54 cpu_load_tlb(env); in helper_ldtlb()
59 void raise_exception(CPUSH4State *env, int index, in raise_exception() argument
62 CPUState *cs = env_cpu(env); in raise_exception()
68 void helper_raise_illegal_instruction(CPUSH4State *env) in helper_raise_illegal_instruction() argument
70 raise_exception(env, 0x180, 0); in helper_raise_illegal_instruction()
73 void helper_raise_slot_illegal_instruction(CPUSH4State *env) in helper_raise_slot_illegal_instruction() argument
75 raise_exception(env, 0x1a0, 0); in helper_raise_slot_illegal_instruction()
78 void helper_raise_fpu_disable(CPUSH4State *env) in helper_raise_fpu_disable() argument
[all …]
/openbmc/qemu/target/xtensa/
H A Dhelper.h1 DEF_HELPER_2(exception, noreturn, env, i32)
2 DEF_HELPER_3(exception_cause, noreturn, env, i32, i32)
3 DEF_HELPER_4(exception_cause_vaddr, noreturn, env, i32, i32, i32)
4 DEF_HELPER_3(debug_exception, noreturn, env, i32, i32)
6 DEF_HELPER_1(sync_windowbase, void, env)
7 DEF_HELPER_4(entry, void, env, i32, i32, i32)
8 DEF_HELPER_2(test_ill_retw, void, env, i32)
9 DEF_HELPER_2(test_underflow_retw, void, env, i32)
10 DEF_HELPER_2(retw, void, env, i32)
11 DEF_HELPER_3(window_check, noreturn, env, i32, i32)
[all …]
/openbmc/qemu/target/s390x/
H A Dhelper.h1 DEF_HELPER_2(exception, noreturn, env, i32)
2 DEF_HELPER_2(data_exception, noreturn, env, i32)
3 DEF_HELPER_FLAGS_4(nc, TCG_CALL_NO_WG, i32, env, i32, i64, i64)
4 DEF_HELPER_FLAGS_4(oc, TCG_CALL_NO_WG, i32, env, i32, i64, i64)
5 DEF_HELPER_FLAGS_4(xc, TCG_CALL_NO_WG, i32, env, i32, i64, i64)
6 DEF_HELPER_FLAGS_4(mvc, TCG_CALL_NO_WG, void, env, i32, i64, i64)
7 DEF_HELPER_FLAGS_4(mvcrl, TCG_CALL_NO_WG, void, env, i64, i64, i64)
8 DEF_HELPER_FLAGS_4(mvcin, TCG_CALL_NO_WG, void, env, i32, i64, i64)
9 DEF_HELPER_FLAGS_4(clc, TCG_CALL_NO_WG, i32, env, i32, i64, i64)
10 DEF_HELPER_3(mvcl, i32, env, i32, i32)
[all …]
/openbmc/qemu/accel/tcg/
H A Dldst_common.c.inc15 tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr,
19 return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD);
22 tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr,
26 return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD);
29 tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr,
33 return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD);
36 uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr,
40 return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD);
48 tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr,
51 return (int8_t)helper_ldub_mmu(env, addr, oi, retaddr);
[all …]
/openbmc/qemu/target/s390x/tcg/
H A Dfpu_helper.c61 static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr) in handle_exceptions() argument
67 qemu_exc = env->fpu_status.float_exception_flags; in handle_exceptions()
71 env->fpu_status.float_exception_flags = 0; in handle_exceptions()
83 !((env->fpc >> 24) & S390_IEEE_MASK_UNDERFLOW)) { in handle_exceptions()
103 if (s390_exc & ~S390_IEEE_MASK_INEXACT & env->fpc >> 24) { in handle_exceptions()
105 tcg_s390_data_exception(env, s390_exc, retaddr); in handle_exceptions()
108 env->fpc |= (s390_exc & ~S390_IEEE_MASK_INEXACT) << 16; in handle_exceptions()
114 if (s390_exc & S390_IEEE_MASK_INEXACT & env->fpc >> 24) { in handle_exceptions()
115 tcg_s390_data_exception(env, s390_exc & S390_IEEE_MASK_INEXACT, in handle_exceptions()
119 env->fpc |= (s390_exc & S390_IEEE_MASK_INEXACT) << 16; in handle_exceptions()
[all …]
/openbmc/qemu/target/hexagon/
H A Dop_helper.c39 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, in hexagon_raise_exception_err() argument
43 CPUState *cs = env_cpu(env); in hexagon_raise_exception_err()
49 G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp) in HELPER()
51 hexagon_raise_exception_err(env, excp, 0); in HELPER()
54 void log_store32(CPUHexagonState *env, target_ulong addr, in log_store32() argument
57 env->mem_log_stores[slot].va = addr; in log_store32()
58 env->mem_log_stores[slot].width = width; in log_store32()
59 env->mem_log_stores[slot].data32 = val; in log_store32()
62 void log_store64(CPUHexagonState *env, target_ulong addr, in log_store64() argument
65 env->mem_log_stores[slot].va = addr; in log_store64()
[all …]
/openbmc/qemu/target/mips/
H A Dcpu.c66 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) in fpu_dump_state() argument
69 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); in fpu_dump_state()
73 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, in fpu_dump_state()
74 get_float_exception_flags(&env->active_fpu.fp_status)); in fpu_dump_state()
77 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); in fpu_dump_state()
83 CPUMIPSState *env = cpu_env(cs); in mips_cpu_dump_state() local
89 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], in mips_cpu_dump_state()
90 env->hflags, env->btarget, env->bcond); in mips_cpu_dump_state()
96 regnames[i], env->active_tc.gpr[i]); in mips_cpu_dump_state()
104 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); in mips_cpu_dump_state()
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