Searched full:either (Results 1 – 25 of 8255) sorted by relevance
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6 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads …12 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads …18 …ded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads …24 …n": "The processor's data cache was reloaded from local core's L2 due to either only demand loads …36 …cache was reloaded from a location other than the local core's L2 due to either only demand loads …42 …he was reloaded from local core's L2 with load hit store conflict due to either only demand loads …48 …ta cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads …54 …from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads …60 …r's data cache was reloaded from local core's L2 without conflict due to either only demand loads …66 …n": "The processor's data cache was reloaded from local core's L3 due to either only demand loads …[all …]
90 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fet…96 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fet…102 …ded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fet…108 …ed from another chip's memory on the same Node or Group (Distant) due to either an instruction fet…114 …e processor's Instruction cache was reloaded from local core's L2 due to either an instruction fet…120 …cache was reloaded from a location other than the local core's L2 due to either an instruction fet…126 …he was reloaded from local core's L2 with load hit store conflict due to either an instruction fet…132 …on cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fet…138 …rom local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fet…144 …truction cache was reloaded from local core's L2 without conflict due to either an instruction fet…[all …]
35 …"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump …65 …"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too sma…365 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for either de…371 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or da…372 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads …377 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or da…378 …p's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads …383 …ded from another chip's L4 on a different Node or Group (Distant) due to either demand loads or da…384 …ded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads …389 …ed from another chip's memory on the same Node or Group (Distant) due to either demand loads or da…[all …]
18 …ed from another chip's memory on the same Node or Group (Distant) due to either only demand loads …24 … processor's data cache was reloaded from the local chip's Memory due to either only demand loads …30 … from a memory location including L4 from local remote or distant due to either only demand loads …36 …loaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads …42 …ed from another chip's memory on the same Node or Group ( Remote) due to either only demand loads …53 …"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump …83 …"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too sma…119 …"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump …203 …"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too sma…
130 * Return: Returns status, either success or error+reason160 * Return: Returns status, either success or error+reason236 * Return: Returns status, either success or error+reason256 * Return: Returns status, either success or error+reason317 * Return: Returns status, either success or error+reason364 * Return: Returns status, either success or error+reason415 * Return: Returns status, either success or error+reason447 * Return: Returns status, either success or error+reason504 * Return: Returns status, either success or error+reason529 * Return: Returns status, either success or error+reason[all …]
28 either builtin or as a module.44 either builtin or as a module.62 by either the generic implementation or an arch-specific one, if one70 either builtin or as a module.88 fulfilled by either the generic implementation or an arch-specific106 either builtin or as a module.123 by either the generic implementation or an arch-specific one, if one
13 Enable automatic brightness control: contains either 0 or 1. If22 WLAN subsystem enabled: contains either 0 or 1.29 Bluetooth subsystem enabled: contains either 0 or 1. Please38 Contains either 0 or 1 and indicates if touchpad is turned on.46 Contains either 0 or 1 and indicates if turbo mode is turned59 Contains either 0 or 1 and indicates if ECO mode is turned on.80 Contains either 0 or 1 and indicates if fan speed is controlled
2 directory = either-1.12.03 source_url = https://crates.io/api/v1/crates/either/1.12.0/download4 source_filename = either-1.12.0.tar.gz7 patch_directory = either-1-rs
25 /* add it to skb. We now have either &skb->len or\ in variable_offset_ctx_access()51 /* add it to fp. We now have either fp-4 or fp-8, but\ in stack_read_priv_vs_unpriv()74 /* add it to fp. We now have either fp-4 or fp-8, but\ in variable_offset_stack_read_uninitialized()105 /* Add it to fp. We now have either fp-8 or \ in stack_write_priv_vs_unpriv()143 /* Add it to fp. We now have either fp-8 or fp-16, but\ in stack_write_followed_by_read()185 /* Add it to fp. We now have either fp-8 or fp-16, but\ in stack_write_clobbers_spilled_regs()251 /* add it to fp. We now have either fp-4 or fp-8, but\ in access_max_out_of_bound()280 /* add it to fp. We now have either fp-516 or fp-512, but\ in access_min_out_of_bound()310 /* Add it to fp. We now have either fp-12 or fp-16, but we don't know\ in access_min_off_min_initialized()343 /* Add it to fp. We now have either fp-12 or fp-16, we don't know\ in stack_access_priv_vs_unpriv()[all …]
15 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…24 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…33 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…42 …r of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credi…51 …r of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credi…60 …r of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credi…69 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…78 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…87 … on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must fir…
15 "BriefDescription": "Cycles in which Superslice 0 dispatches either 1 or 2 instructions."45 "BriefDescription": "Cycles in which Superslice 1 dispatches either 1 or 2 instructions."50 "BriefDescription": "Cycles in which Superslice 1 dispatches either 3 or 4 instructions."75 "BriefDescription": "Cycles in which Superslice 0 dispatches either 3 or 4 instructions."80 "BriefDescription": "Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions."
586 …code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit…631 …ch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the …640 …data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit…676 …ch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the …685 …code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit…721 …ch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the …730 …data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit…766 …prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the …775 …fetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit…820 …d & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the …[all …]
1 project('either-1-rs', 'rust',8 'either',25 meson.override_dependency('either-1-rs', either_dep, native: true)
90 * active) or as a halfplex (either the Tx data path is108 * active) or as a halfplex (either the Tx data path is177 * active) or as a halfplex (either the Tx data path is193 * active) or as a halfplex (either the Tx data path is210 * active) or as a halfplex (either the Tx data path is227 * active) or as a halfplex (either the Tx data path is244 * active) or as a halfplex (either the Tx data path is261 * active) or as a halfplex (either the Tx data path is
55 Intermediate Frequency Mode Enable. Either IF Mode or I/Q Mode61 I/Q Mode Enable. Either IF Mode or I/Q Mode can be enabled at a68 Oscillator Input Frequency. Either LOx1 or LOx2 can be enabled75 output frequency (LO x1). Either LOx1 or LOx2 can be enabled
109 This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]121 This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]216 Tegra194. This controller can work either as EP or RC. In order to231 Tegra194. This controller can work either as EP or RC. In order to248 This controller can work either as EP or RC. In order to enable263 This controller can work either as EP or RC. In order to enable362 This controller can work either as EP or RC. In order to enable377 This controller can work either as EP or RC. In order to enable
41 "description": "Either read or write.",46 "description": "Either Translated or untranslated address",51 "description": "Either VT-d or IOMMU",
16 /// - `ptr` can be either null or a pointer which has been allocated by this allocator.35 // - `ptr` is either null or a pointer returned from a previous `k{re}alloc()` by the in krealloc_aligned()37 // - `size` is greater than 0 since it's either a `layout.size()` (which cannot be zero in krealloc_aligned()63 // - `ptr` is either null or a pointer allocated by this allocator by the function safety in realloc()
23 * - the ISA bit of the target, either 0 or 1 respectively,26 * immediate field of the machine instruction, either 2 or 1,29 * delay-slot instruction, either 256MB or 128MB,31 * - the jump target alignment, either 4 or 2 bytes.
5 …nt rights owned or freely licensable by each licensor hereunder covering either (i) the unmodified…11 …ftware and the Larger Work(s), and to sublicense the foregoing rights on either these or other ter…15 The above copyright notice and either this complete permission notice or at a minimum a reference t…
26 signals, which are either directly wired to the consumers (like37 SoC. CCU dividers can be either configurable or with fixed divider,38 either gateable or ungateable. Some of the CCU dividers can be as well
33 Either, enumerator73 {ThresholdActivation::Either, "Either"},
163 * either zero or negative errno. Called with pib_lock held.168 * Returns either zero, or negative errno. Called with pib_lock held.173 * Returns either zero, or negative errno.177 * Returns either zero, or negative errno.182 * Returns either zero, or negative errno.186 * Returns either zero, or negative errno.191 * Returns either zero, or negative errno.195 * Returns either zero, or negative errno.199 * Returns either zero, or negative errno.
21 # Either a single combined interrupt or up to 14 individual interrupts43 # Either a single combined interrupt or up to 6 individual interrupts57 # Either a single combined interrupt or up to 4 individual interrupts69 timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
18 * configure it to either pass through or reject transactions.19 * Rejected transactions may be configured to either be aborted, or to24 * they are either hardwired or exposed in an ad-hoc register interface by27 * This QEMU model can be used to model either the AHB5 or APB4 TZ PPC,