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/openbmc/linux/drivers/dma/
H A Dmcf-edma-main.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/platform_data/dma-mcf-edma.h>
12 #include "fsl-edma-common.h"
20 struct edma_regs *regs = &mcf_edma->regs; in mcf_edma_tx_handler()
24 intmap = ioread32(regs->inth); in mcf_edma_tx_handler()
26 intmap |= ioread32(regs->intl); in mcf_edma_tx_handler()
30 for (ch = 0; ch < mcf_edma->n_chans; ch++) { in mcf_edma_tx_handler()
32 iowrite8(EDMA_MASK_CH(ch), regs->cint); in mcf_edma_tx_handler()
33 fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]); in mcf_edma_tx_handler()
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H A Dep93xx_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * arch/arm/mach-ep93xx/dma-m2p.c which has following copyrights:
14 * This driver is based on dw_dmac and amba-pl08x drivers.
26 #include <linux/platform_data/dma-ep93xx.h>
113 * struct ep93xx_dma_desc - EP93xx specific transaction descriptor
133 * struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel
135 * @edma: pointer to the engine device
166 const struct ep93xx_dma_engine *edma; member
187 * struct ep93xx_dma_engine - the EP93xx DMA engine instance
221 return &edmac->chan.dev->device; in chan2dev()
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H A Dfsl-edma-main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
12 #include <dt-bindings/dma/fsl-edma.h>
22 #include <linux/dma-mapping.h>
26 #include "fsl-edma-common.h"
32 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
39 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
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H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/dma-mapping.h>
14 #include "fsl-edma-common.h"
48 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
50 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
52 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
56 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
57 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
58 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
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/openbmc/u-boot/arch/arm/dts/
H A Ddm816x.dtsi7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/omap.h>
12 interrupt-parent = <&intc>;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
31 compatible = "arm,cortex-a8";
38 compatible = "arm,cortex-a8-pmu";
47 compatible = "ti,omap-infra";
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H A Dam33xx.dtsi4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/am33xx.h>
13 #include <dt-bindings/clock/am3.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 d-can0 = &dcan0;
33 d-can1 = &dcan1;
45 #address-cells = <1>;
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H A Dam4372.dtsi4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&wakeupgen>;
32 #address-cells = <1>;
33 #size-cells = <0>;
35 compatible = "arm,cortex-a9";
40 clock-names = "cpu";
42 clock-latency = <300000>; /* From omap-cpufreq driver */
46 gic: interrupt-controller@48241000 {
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H A Dls1021a.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a7";
37 compatible = "arm,cortex-a7";
45 compatible = "arm,armv7-timer";
53 compatible = "arm,cortex-a7-pmu";
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dti-edma.txt1 Texas Instruments eDMA
8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
21 - reg-names: "edma3_cc"
22 - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
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H A Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
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H A Dti-dma-crossbar.txt4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
13 - dma-requests: Number of DMA requests the controller can handle
16 - ti,dma-safe-map: Safe routing value for unused request lines
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
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/openbmc/linux/arch/m68k/coldfire/
H A Ddevice.c2 * device.c -- common ColdFire SoC device support
23 #include <linux/platform_data/edma.h>
24 #include <linux/platform_data/dma-mcf-edma.h>
25 #include <linux/platform_data/mmc-esdhc-mcf.h>
99 #define FEC_NAME "enet-fec"
117 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
154 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
195 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
346 .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
357 .name = "imx1-i2c",
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddm816x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/bus/ti-sysc.h>
4 #include <dt-bindings/clock/dm816.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/omap.h>
10 interrupt-parent = <&intc>;
11 #address-cells = <1>;
12 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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H A Ddm814x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/bus/ti-sysc.h>
4 #include <dt-bindings/clock/dm814.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/dm814x.h>
10 interrupt-parent = <&intc>;
11 #address-cells = <1>;
12 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
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H A Dam33xx-l4.dtsi2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
18 compatible = "simple-pm-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
28 compatible = "simple-pm-bus";
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Domap-aes.txt5 - compatible : Should contain entries for this and backward compatible
7 - "ti,omap2-aes" for OMAP2.
8 - "ti,omap3-aes" for OMAP3.
9 - "ti,omap4-aes" for OMAP4 and AM33XX.
12 - ti,hwmods: Name of the hwmod associated with the AES module
13 - reg : Offset and length of the register set for the module
14 - interrupts : the interrupt-specifier for the AES module.
17 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
19 - dma-names: DMA request names should include "tx" and "rx" if present.
24 compatible = "ti,omap4-aes";
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/openbmc/linux/sound/soc/ti/
H A Dedma-pcm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * edma-pcm.c - eDMA PCM driver using dmaengine for AM3xxx, AM4xxx
19 #include "edma-pcm.h"
31 .periods_max = 19, /* Limit by edma dmaengine driver */
44 if (dev->of_node) in edma_pcm_platform_register()
50 return -ENOMEM; in edma_pcm_platform_register()
54 config->chan_names[0] = "tx"; in edma_pcm_platform_register()
55 config->chan_names[1] = "rx"; in edma_pcm_platform_register()
62 MODULE_DESCRIPTION("eDMA PCM ASoC platform driver");
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Ddavinci_mmc.txt9 - compatible:
10 Should be "ti,da830-mmc": for da830, da850, dm365
11 Should be "ti,dm355-mmc": for dm355, dm644x
14 - bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1>
15 - max-frequency: Maximum operating clock frequency, default 25MHz.
16 - dmas: List of DMA specifiers with the controller specific format
17 as described in the generic DMA client binding. A tx and rx
19 - dma-names: RX and TX DMA request names. These strings correspond
24 compatible = "ti,da830-mmc",
27 bus-width = <4>;
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H A Dti-omap-hsmmc.txt10 --------------------
11 - compatible:
12 Should be "ti,omap2-hsmmc", for OMAP2 controllers
13 Should be "ti,omap3-hsmmc", for OMAP3 controllers
14 Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
15 Should be "ti,omap4-hsmmc", for OMAP4 controllers
16 Should be "ti,am33xx-hsmmc", for AM335x controllers
17 Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
20 ---------------------------------
22 - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
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/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "vf610-pinfunc.h"
6 #include <dt-bindings/clock/vf610-clock.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
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/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
16 #include <linux/dma/edma.h>
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
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/openbmc/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI EDMA DMA engine driver
9 #include <linux/dma-mapping.h>
25 #include <linux/platform_data/edma.h>
28 #include "../virt-dma.h"
42 /* Offsets for EDMA CC global channel registers and their shadows */
66 /* Offsets for EDMA CC global registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
100 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
101 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
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/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/keystone.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
32 #address-cells = <1>;
33 #size-cells = <0>;
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