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/openbmc/linux/Documentation/driver-api/
H A Dedac.rst5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
28 called DIMM (Dual Inline Memory Module).
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Software/
H A DRedundancyPriority.interface.yaml5 - name: Priority
10 above 127 has implementation-specific purpose.
16 A dual-sided redundancy model could be represented by two
19 priority-1 association is deleted, the old priority-0 association
20 becomes priority-1, and the new image is assigned priority-0.
/openbmc/linux/drivers/edac/
H A De752x_edac.c10 * https://www.intel.in/content/www/in/en/chipsets/e7525-memory-controller-hub-datasheet.html
33 static int sysbus_parity = -1;
77 /* E752X register addresses - device 0 function 0 */
108 * 14:12 1 single A, 2 single B, 3 dual
115 /* E752X register addresses - device 0 function 1 */
173 /* 3100 IMCH specific register addresses - device 0 function 1 */
179 /* ICH5R register addresses - device 30 function 0 */
192 * Those chips Support single-rank and dual-rank memories only.
194 * On e752x chips, the odd rows are present only on dual-rank memories.
200 * slot single-ranked double-ranked
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/openbmc/linux/drivers/net/wireless/ti/wlcore/
H A Dacx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
6 * Copyright (C) 2008-2010 Nokia Corporation
19 Host Interrupt Register (WiLink -> Host)
45 /* all possible interrupts - only appropriate ones will be masked in */
119 /* 0 - Always active*/
120 /* 1 - Power down mode: light / fast sleep*/
121 /* 2 - ELP mode: Deep / Max sleep*/
246 * Treatment bit mask - The information element handling:
247 * bit 0 - The information element is compared and transferred
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