| /openbmc/linux/drivers/ata/ |
| H A D | ahci_dwc.c | 122 u32 dmacr[AHCI_MAX_PORTS]; member
265 u32 port, dmacr, ts; in ahci_dwc_init_dmacr() local
284 dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr()
288 dmacr &= ~AHCI_DWC_PORT_TXTS_MASK; in ahci_dwc_init_dmacr()
289 dmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts); in ahci_dwc_init_dmacr()
294 dmacr &= ~AHCI_DWC_PORT_RXTS_MASK; in ahci_dwc_init_dmacr()
295 dmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts); in ahci_dwc_init_dmacr()
298 writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr()
299 dpriv->dmacr[port] = dmacr; in ahci_dwc_init_dmacr()
361 writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_reinit_host()
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| H A D | sata_dwc_460ex.c | 58 u32 dmacr; /* DMA Control */ member
689 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr); in sata_dwc_clear_dmacr() local
692 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr); in sata_dwc_clear_dmacr()
693 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr); in sata_dwc_clear_dmacr()
695 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr); in sata_dwc_clear_dmacr()
696 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr); in sata_dwc_clear_dmacr()
700 * sync. If it does happen, clear dmacr anyway. in sata_dwc_clear_dmacr()
703 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n", in sata_dwc_clear_dmacr()
704 __func__, tag, hsdevp->dma_pending[tag], dmacr); in sata_dwc_clear_dmacr()
705 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, in sata_dwc_clear_dmacr()
[all …]
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| /openbmc/linux/drivers/tty/serial/ |
| H A D | amba-pl011.c | 259 unsigned int dmacr; /* dma control reg */ member
545 u16 dmacr; in pl011_dma_tx_callback() local
552 dmacr = uap->dmacr; in pl011_dma_tx_callback()
553 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
554 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
563 * get further refills (hence we check dmacr). in pl011_dma_tx_callback()
565 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
668 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
669 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
703 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/display/imx/ |
| H A D | fsl,imx-lcdc.yaml | 53 fsl,dmacr:
79 fsl,dmacr: false
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| /openbmc/u-boot/drivers/spi/ |
| H A D | lpc32xx_ssp.c | 27 u32 dmacr; member
90 writel(0, &lslave->regs->dmacr); /* do not do DMAs */ in spi_setup_slave()
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| H A D | rk_spi.h | 30 u32 dmacr; member
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| H A D | rk_spi.c | 67 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); in rkspi_dump_regs()
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| /openbmc/linux/sound/soc/fsl/ |
| H A D | p1022_rdk.c | 41 * Set the DMACR register in the GUTS
43 * The DMACR register determines the source of initiated transfers for each
87 * Here we program the DMACR and PMUXCR registers.
159 * de-program the DMACR and PMUXCR register.
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| H A D | p1022_ds.c | 34 * Set the DMACR register in the GUTS
36 * The DMACR register determines the source of initiated transfers for each
81 * Here we program the DMACR and PMUXCR registers.
155 * de-program the DMACR and PMUXCR register.
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| H A D | mpc8610_hpcd.c | 49 * Here we program the DMACR and PMUXCR registers.
133 * de-program the DMACR and PMUXCR register.
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| /openbmc/qemu/rust/hw/char/pl011/src/ |
| H A D | device.rs | 72 pub dmacr: u32, field
230 Ok(DMACR) => self.dmacr.into(), in read()
317 Ok(DMACR) => { in write()
318 self.dmacr = value; in write()
429 self.dmacr = 0; in reset()
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| H A D | device_class.rs | 59 vmstate_uint32!(dmacr, PL011State),
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| /openbmc/linux/include/linux/fsl/ |
| H A D | guts.h | 106 u32 dmacr; /* 0x.0908 - DMA Control Register */ member
143 * Set the DMACR register in the GUTS
145 * The DMACR register determines the source of initiated transfers for each
160 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); in guts_set_dmacr()
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| /openbmc/qemu/hw/char/ |
| H A D | pl011.c | 108 [15] = "RIS", [16] = "MIS", [17] = "ICR", [18] = "DMACR", in pl011_regname()
314 r = s->dmacr; in pl011_read()
474 s->dmacr = value; in pl011_write()
587 VMSTATE_UINT32(dmacr, PL011State),
644 s->dmacr = 0; in pl011_reset()
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| /openbmc/linux/sound/soc/rockchip/ |
| H A D | rockchip_spdif.h | 33 * DMACR
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| /openbmc/qemu/include/hw/char/ |
| H A D | pl011.h | 39 uint32_t dmacr; member
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | imxfb.c | 186 u_int dmacr; member
679 /* dmacr = 0 is no valid value, as we need DMA control marks. */ in imxfb_activate_var()
680 if (fbi->dmacr) in imxfb_activate_var()
681 writel(fbi->dmacr, fbi->regs + LCDC_DMACR); in imxfb_activate_var()
737 of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr); in imxfb_init_fbinfo()
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-rockchip.c | 146 /* Bit fields in DMACR */
535 u32 dmacr = 0; in rockchip_spi_config() local
580 dmacr |= TF_DMA_EN; in rockchip_spi_config()
582 dmacr |= RF_DMA_EN; in rockchip_spi_config()
600 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); in rockchip_spi_config()
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| H A D | spi-pl022.c | 408 * @dmacr: Value of DMA control Register of SSP
422 u16 dmacr; member
561 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); in restore_state()
1489 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); in print_current_status()
1964 chip->dmacr = 0; in pl022_setup()
1970 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1972 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1977 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1979 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
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| /openbmc/qemu/hw/ssi/ |
| H A D | pl022.c | 152 case 0x24: /* DMACR */ in pl022_read()
206 case 0x24: /* DMACR */ in pl022_write()
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| /openbmc/linux/drivers/dma/xilinx/ |
| H A D | xilinx_dma.c | 2539 u32 dmacr; in xilinx_vdma_channel_set_config() local
2544 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_channel_set_config()
2553 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; in xilinx_vdma_channel_set_config()
2555 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; in xilinx_vdma_channel_set_config()
2556 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; in xilinx_vdma_channel_set_config()
2557 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; in xilinx_vdma_channel_set_config()
2572 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; in xilinx_vdma_channel_set_config()
2573 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; in xilinx_vdma_channel_set_config()
2578 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; in xilinx_vdma_channel_set_config()
2579 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; in xilinx_vdma_channel_set_config()
[all …]
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| /openbmc/u-boot/drivers/sound/ |
| H A D | rockchip_i2s.c | 21 u32 dmacr; /* I2S_DMACR, 0x10 */ member
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx27-apf27dev.dts | 94 fsl,dmacr = <0x00020010>;
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| H A D | imx27-eukrea-mbimxsd27-baseboard.dts | 91 fsl,dmacr = <0x00040060>;
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| H A D | imx25-pdk.dts | 242 fsl,dmacr = <0x00020010>;
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