| /openbmc/linux/drivers/dma/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # DMA engine configuration
7 bool "DMA Engine support"
10 DMA engines can do asynchronous data transfers without
14 DMA Device drivers supported by the configured arch, it may
18 bool "DMA Engine debugging"
22 say N here. This enables DMA engine core and driver debugging.
25 bool "DMA Engine verbose debugging"
30 the DMA engine core and drivers.
35 comment "DMA Devices"
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| H A D | of-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device tree helpers for DMA request / controller
7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
24 * of_dma_find_controller - Get a DMA controller in DT DMA helpers list
25 * @dma_spec: pointer to DMA specifier as found in the device tree
27 * Finds a DMA controller with matching device node and number for dma cells
28 * in a list of registered DMA controllers. If a match is found a valid pointer
29 * to the DMA data stored is retuned. A NULL pointer is returned if no match is
37 if (ofdma->of_node == dma_spec->np) in of_dma_find_controller()
40 pr_debug("%s: can't find DMA controller %pOF\n", __func__, in of_dma_find_controller()
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| H A D | acpi-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI helpers for DMA request / controller
5 * Based on of-dma.c
13 #include <linux/dma-mapping.h>
29 * acpi_dma_parse_resource_group - match device and parse resource group
32 * @adma: struct acpi_dma of the given DMA controller
50 if (grp->shared_info_length != sizeof(struct acpi_csrt_shared_info)) in acpi_dma_parse_resource_group()
51 return -ENODEV; in acpi_dma_parse_resource_group()
59 if (resource_type(rentry->res) == IORESOURCE_MEM) in acpi_dma_parse_resource_group()
60 mem = rentry->res->start; in acpi_dma_parse_resource_group()
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-channels: deprecated
16 - dma-requests: Number of DMA requestor lines supported by the controller
18 - #dma-requests: deprecated
20 "marvell,pdma-1.0"
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| H A D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
8 the dma/dma.txt file for a more detailed description of binding.
11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
14 is described in interrupt-controller/interrupts.txt file.
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
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| H A D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: dma-controller.yaml#
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| H A D | sprd-dma.txt | 1 * Spreadtrum DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
6 - compatible: Should be "sprd,sc9860-dma".
7 - reg: Should contain DMA registers location and length.
8 - interrupts: Should contain one interrupt shared by all channel.
9 - #dma-cells: must be <1>. Used to represent the number of integer
11 - dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
13 - clocks: Should contain a clock specifier for each entry in clock-names.
16 - #dma-channels : Number of DMA channels supported. Should be 32.
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| H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused)
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| H A D | apple,admac.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/apple,admac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Audio DMA Controller (ADMAC)
10 Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples
13 The controller has been seen with up to 24 channels. Even-numbered channels
14 are TX-only, odd-numbered are RX-only. Individual channels are coupled to
18 - Martin Povišer <povik+lin@cutebit.org>
21 - $ref: dma-controller.yaml#
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| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
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| H A D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
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| H A D | qcom,gpi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
10 - Vinod Koul <vkoul@kernel.org>
13 QCOM GPI DMA controller provides DMA capabilities for
17 - $ref: dma-controller.yaml#
22 - enum:
23 - qcom,sdm845-gpi-dma
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| H A D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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| H A D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
9 - compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
13 - #dma-cells : Has to be 1. imx-dma does not support anything else.
16 - dma-channels : Number of DMA channels supported. Should be 16.
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| H A D | mediatek,uart-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek UART APDMA controller
10 - Long Cheng <long.cheng@mediatek.com>
13 The MediaTek UART APDMA controller provides DMA capabilities
17 - $ref: dma-controller.yaml#
22 - items:
23 - enum:
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| H A D | atmel-xdma.txt | 1 * Atmel Extensible Direct Memory Access Controller (XDMAC)
3 * XDMA Controller
5 - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
6 "microchip,sama7g5-dma" or
7 "microchip,sam9x7-dma", "atmel,sama5d4-dma".
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Should contain DMA interrupt.
10 - #dma-cells: Must be <1>, used to represent the number of integer cells in
12 - The 1st cell specifies the channel configuration register:
13 - bit 13: SIF, source interface identifier, used to get the memory
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| /openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
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| /openbmc/linux/Documentation/core-api/ |
| H A D | dma-isa-lpc.rst | 2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
8 controller. Even though ISA is more or less dead today the LPC bus
9 uses the same DMA system so it will be around for quite some time.
12 ------------------------
14 To do ISA style DMA you need to include two headers::
16 #include <linux/dma-mapping.h>
17 #include <asm/dma.h>
19 The first is the generic DMA API used to convert virtual addresses to
20 bus addresses (see Documentation/core-api/dma-api.rst for details).
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| /openbmc/linux/drivers/dma/qcom/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 Enable support for the Qualcomm Application Data Mover (ADM) DMA
9 controller, as present on MSM8x60, APQ8064, and IPQ8064 devices.
10 This controller provides DMA capabilities for both general purpose
11 and on-chip peripheral devices.
14 tristate "QCOM BAM DMA support"
19 Enable support for the QCOM BAM DMA controller. This controller
20 provides DMA capabilities for a variety of on-chip devices.
23 tristate "Qualcomm Technologies GPI DMA support"
28 Enable support for the QCOM GPI DMA controller. This controller
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| /openbmc/linux/drivers/dma/sh/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # DMA engine configuration for sh
11 # DMA Engine Helpers
15 bool "Renesas SuperH DMA Engine support"
22 Enable support for the Renesas SuperH DMA controllers.
25 # DMA Controllers
32 Enable support for the Renesas SuperH DMA controllers.
35 tristate "Renesas R-Car Gen{2,3} and RZ/G{1,2} DMA Controller"
39 This driver supports the general purpose DMA controller found in the
40 Renesas R-Car Gen{2,3} and RZ/G{1,2} SoCs.
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| /openbmc/u-boot/drivers/dma/ |
| H A D | lpc32xx_dma.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * @Descr: LPC3250 DMA controller interface support functions
12 #include <asm/arch/dma.h>
18 /* DMA controller channel register structure */
28 /* DMA controller register structures */
51 #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */
55 static struct dma_reg *dma = (struct dma_reg *)DMA_BASE; variable
63 * DMA clock are enable by "lpc32xx_dma_init()" and should in lpc32xx_dma_get_channel()
68 * Make sure DMA controller and all channels are disabled. in lpc32xx_dma_get_channel()
69 * Controller is in little-endian mode. Disable sync signals. in lpc32xx_dma_get_channel()
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| /openbmc/u-boot/drivers/usb/musb-new/ |
| H A D | musb_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * MUSB OTG driver DMA controller abstraction
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
16 * DMA Controller Abstraction
18 * DMA Controllers are abstracted to allow use of a variety of different
19 * implementations of DMA, as allowed by the Inventra USB cores. On the
20 * host side, usbcore sets up the DMA mappings and flushes caches; on the
21 * peripheral side, the gadget controller driver does. Responsibilities
22 * of a DMA controller driver include:
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| H A D | musb_gadget.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
19 #include <linux/dma-mapping.h>
24 #include "linux-compat.h"
30 /* MUSB PERIPHERAL status 3-mar-2006:
32 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
37 * + endpoint halt tests -- in both usbtest and usbcv -- seem
38 * to break when dma is enabled ... is something wrongly
41 * - Mass storage behaved ok when last tested. Network traffic patterns
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| /openbmc/linux/drivers/usb/musb/ |
| H A D | musb_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * MUSB OTG driver DMA controller abstraction
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
16 * DMA Controller Abstraction
18 * DMA Controllers are abstracted to allow use of a variety of different
19 * implementations of DMA, as allowed by the Inventra USB cores. On the
20 * host side, usbcore sets up the DMA mappings and flushes caches; on the
21 * peripheral side, the gadget controller driver does. Responsibilities
22 * of a DMA controller driver include:
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| /openbmc/linux/include/linux/dma/ |
| H A D | sprd-dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
16 * we can request 2 dma channels, one for source channel, and another one for
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
29 * support the 2-stage transfer.
35 * Now the DMA controller can supports 2 groups 2-stage transfer.
46 * enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
56 * automatically once the source channel's link-list request is done.
67 * enum sprd_dma_req_mode: define the DMA request mode
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