Home
last modified time | relevance | path

Searched +full:displayport +full:- +full:controller (Results 1 – 25 of 89) sorted by relevance

1234

/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,dispcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SC8280XP
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
22 - qcom,sc8280xp-dispcc0
23 - qcom,sc8280xp-dispcc1
27 - description: AHB interface clock,
[all …]
H A Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_power.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
12 * sruct dp_power - DisplayPort's power related data
26 * dp_power_init() - enable power supplies for display controller
37 * dp_power_deinit() - turn off regulators and gpios.
47 * dp_power_clk_status() - display controller clocks status
59 * dp_power_clk_enable() - enable display controller clocks
73 * dp_power_client_init() - initialize clock and regulator modules
78 * This API will configure the DisplayPort's clocks and regulator
84 * dp_power_clinet_deinit() - de-initialize clock and regulator modules
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DProtocol.json3 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
4 "copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright",
41 "DisplayPort",
52 "AHCI": "Advanced Host Controller Interface (AHCI).",
55 "DisplayPort": "DisplayPort.",
66 "I2C": "Inter-Integrated Circuit Bus.",
72 "NVMe": "Non-Volatile Memory Express (NVMe).",
74 "OEM": "OEM-specifi
54 "DisplayPort": "DisplayPort.", global() string
97 "DisplayPort": "This value shall indicate conformance to the VESA DisplayPort Specification.", global() string
138 "DisplayPort": "2021.1", global() string
[all...]
/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-dpaux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra DisplayPort AUX Interface
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
16 controller.
18 When configured for DisplayPort AUX operation, the DPAUX controller
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DProtocol.json3 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
4 …"copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
41 "DisplayPort",
52 "AHCI": "Advanced Host Controller Interface (AHCI).",
55 "DisplayPort": "DisplayPort.", string
66 "I2C": "Inter-Integrated Circuit Bus.",
72 "NVMe": "Non-Volatile Memory Express (NVMe).",
74 "OEM": "OEM-specific.",
87 "UHCI": "Universal Host Controller Interface (UHCI).",
96 …CI": "This value shall indicate conformance to the Intel Advanced Host Controller Interface (AHCI)…
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11 implements the display and audio pipelines based on the DisplayPort v1.2
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSM Display Port Controller
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort interface specification.
19 - enum:
20 - qcom,sc7180-dp
[all …]
H A Dqcom,sc7180-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7180-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
[all …]
H A Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: ../dma-controller.yaml#
22 "#dma-cells":
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
[all …]
/openbmc/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dpsub.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
43 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
55 * @disp: The display controller
56 * @dp: The DisplayPort controller
/openbmc/linux/drivers/gpu/drm/bridge/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
26 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
50 ChromeOS EC ANX7688 is an ultra-low power
51 4K Ultra-HD (4096x2160p60) mobile HD transmitter
53 2.0 to DisplayPort 1.3 Ultra-HD. It is connected
54 to the ChromeOS Embedded Controller.
60 Driver for display connectors with support for DDC and hot-plug
64 on ARM-based platforms. Saying Y here when this driver is not needed
74 Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Ddp-aux-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DisplayPort AUX bus
10 - Douglas Anderson <dianders@chromium.org>
13 DisplayPort controllers provide a control channel to the sinks that
20 of the DP controller under the "aux-bus" node.
29 const: aux-bus
32 $ref: panel/panel-common.yaml#
[all …]
/openbmc/u-boot/include/dm/
H A Duclass-id.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 /* TODO(sjg@chromium.org): this could be compile-time generated */
29 /* U-Boot uclasses start here - in alphabetical order */
30 UCLASS_ADC, /* Analog-to-digital converter */
31 UCLASS_AHCI, /* SATA disk controller */
40 UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
46 UCLASS_GPIO, /* Bank of general-purpose I/O pins */
54 UCLASS_IRQ, /* Interrupt controller */
56 UCLASS_LED, /* Light-emitting diode (LED) */
58 UCLASS_MAILBOX, /* Mailbox controller */
[all …]
/openbmc/linux/sound/pci/hda/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "HD-Audio"
23 This option enables the HD-audio controller. Don't forget
27 will be called snd-hda-intel.
35 Say Y here to support the HDA controller present in NVIDIA
38 This options enables support for the HD Audio controller
43 will be called snd-hda-tegra.
48 bool "Build hwdep interface for HD-audio driver"
51 Say Y here to build a hwdep interface for HD-audio driver.
52 This interface can be used for out-of-band communication
[all …]
/openbmc/u-boot/drivers/video/rockchip/
H A DKconfig8 # Author: Eric Gao <eric.gao@rock-chips.com>
15 Rockchip SoCs provide video output capabilities for High-Definition
16 Multimedia Interface (HDMI), Low-voltage Differential Signalling
17 (LVDS), embedded DisplayPort (eDP) and Display Serial Interface (DSI).
19 This driver supports the on-chip video output device, and targets the
29 framebuffer during device-model binding/probing.
38 framebuffer during device-model binding/probing.
46 This enables Embedded DisplayPort(EDP) display support.
52 This enables Low-voltage Differential Signaling(LVDS) display
60 This enables High-Definition Multimedia Interface display support.
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
51 based PCIe controller.
69 with USB3 and DisplayPort controllers on Qualcomm chips.
110 Enable this legacy driver to support the QMP USB+DisplayPort Combo
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
134 chipsets. The PHY is paired with a Synopsys DWC3 USB controller
142 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
160 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
[all …]
/openbmc/linux/Documentation/gpu/
H A Dtegra.rst6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
22 outputs, such as RGB, HDMI, DSI, and DisplayPort.
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
[all …]
/openbmc/linux/Documentation/gpu/amdgpu/display/
H A Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
39 * DCFCLK: Display Controller Fabric Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
62 Display Controller
68 Display Controller Engine
71 Display Controller HUB
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
114 DisplayPort Configuration Data
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dite,it6505.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen Chen <allen.chen@ite.com.tw>
13 The IT6505 is a high-performance DisplayPort 1.1a transmitter,
14 fully compliant with DisplayPort 1.1a, HDCP 1.3 specifications.
16 and ensures robust transmission of high-quality uncompressed video
27 transmission of high-definition content. Users of the IT6505 need not
37 ovdd-supply:
40 pwr18-supply:
[all …]
/openbmc/linux/drivers/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
65 Enable support for Altera / Intel mSGDMA controller.
94 Enable support for Audio DMA Controller found on Apple Silicon SoCs.
102 Support the Atmel AHB DMA controller.
109 Support the Atmel XDMA controller.
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
119 controller is often used in Analog Devices' reference designs for FPGA
149 This selects support for the DMA controller in Ingenic JZ4780 SoCs.
151 devices which can use the DMA controller, say Y or M here.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dsamsung,dp-video-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC DisplayPort PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
17 - samsung,exynos5250-dp-video-phy
18 - samsung,exynos5420-dp-video-phy
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/connector/
H A Ddp-connector.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/connector/dp-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DisplayPort Connector
10 - Tomi Valkeinen <tomi.valkeinen@ti.com>
14 const: dp-connector
20 - full-size
21 - mini
23 hpd-gpios:
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
16 - reset-names: Must include the following entries:
[all …]

1234