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/openbmc/u-boot/include/
H A Ddisplay.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 * Display uclass platform data for each device
15 * @source_id: ID for the source of the display data, typically a video
18 * @in_use: Display is being used
27 * display_read_timing() - Read timing information
30 * @return 0 if OK, -ve on error
32 int display_read_timing(struct udevice *dev, struct display_timing *timing);
35 * display_port_enable() - Enable a display port device
39 * @timing: Display timings
40 * @return 0 if OK, -ve on error
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/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Ddisplay-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/display-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: display timings
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
12 - Sam Ravnborg <sam@ravnborg.org>
15 A display panel may be able to handle several display timings,
17 The display-timings node makes it possible to specify the timings
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H A Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Display Panels
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
15 display panels. It doesn't constitute a device tree binding specification by
24 width-mm:
29 height-mm:
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H A Dpanel-mipi-dbi-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Noralf Trønnes <noralf@tronnes.org>
13 This binding is for display panels using a MIPI DBI compatible controller
16 The MIPI Alliance Standard for Display Bus Interface defines the electrical
17 and logical interfaces for display controllers historically used in mobile
18 phones. The standard defines 4 display architecture types and this binding is
23 - Power:
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H A Dsgd,gktw70sdae4se.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/sgd,gktw70sdae4se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
24 - compatible
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H A Dadvantech,idk-1110wr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-1110wr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Advantech IDK-1110WR 10.1" WSVGA LVDS Display Panel
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
21 const: advantech,idk-1110wr
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H A Dmitsubishi,aa104xd12.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/mitsubishi,aa104xd12.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mitsubishi AA104XD12 10.4" XGA LVDS Display Panel
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
24 - compatible
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H A Dmitsubishi,aa121td01.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/mitsubishi,aa121td01.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mitsubishi AA121TD01 12.1" WXGA LVDS Display Panel
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
24 - compatible
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/openbmc/openbmc/meta-nuvoton/recipes-nuvoton/program-edid/program-edid/
H A Dedid.json3 "Basic Display": {
8 "DPM active-off supported": true,
12 "Display color type": "RGB 4:4:4 + YCrCb 4:4:4",
13 "Display gamma": 2.2,
18 "Preferred timing includes native timing pixel format and refresh rate": true,
70 "Horizontal sync (outside of V-sync)": "Positive",
74 "Type": "Detailed Timing Descriptor"
105 "Horizontal sync (outside of V-sync)": "Positive",
109 "Type": "Detailed Timing Descriptor"
118 "Type": "Display Range Limits Descriptor",
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/openbmc/linux/Documentation/gpu/amdgpu/display/
H A Ddc-glossary.rst5 On this page, we try to keep track of acronyms related to the display
7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
37 * DISPCLK: Display Clock
39 * DCFCLK: Display Controller Fabric Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
56 Display Abstraction layer
59 Display Core
62 Display Controller
68 Display Controller Engine
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/openbmc/linux/drivers/video/backlight/
H A Dtdo24m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
45 #define CMD_NULL (-1)
56 CMD0(0x29), /* Display ON */
64 CMD0(0x28), /* Display OFF */
92 CMD1(0xd1, 0x01), /* CKV timing control on/off */
93 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
94 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
95 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
96 CMD1(0xd5, 0x14), /* ASW timing control (2) */
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Ddisplay-timing.txt1 display-timing bindings
4 display-timings node
5 --------------------
8 - none
11 - native-mode: The native mode for the display, in case multiple modes are
14 timing subnode
15 --------------
18 - hactive, vactive: display resolution
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
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H A Ddisplaymode.txt4 (from http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html)
7 - xres, yres: Display resolution
8 - left-margin, right-margin, hsync-len: Horizontal Display timing
10 - upper-margin, lower-margin, vsync-len: Vertical display timing
12 - clock: display clock in Hz
15 - width-mm, height-mm: Display dimensions in mm
16 - hsync-active-high (bool): Hsync pulse is active high
17 - vsync-active-high (bool): Vsync pulse is active high
18 - interlaced (bool): This is an interlaced mode
19 - doublescan (bool): This is a doublescan mode
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/openbmc/u-boot/drivers/video/tegra124/
H A Ddisplay.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <display.h>
20 #include <asm/arch-tegra/dc.h>
21 #include <dm/uclass-internal.h>
25 static int tegra_dc_calc_refresh(const struct display_timing *timing) in tegra_dc_calc_refresh() argument
28 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
30 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
31 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
32 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
33 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
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/openbmc/u-boot/drivers/video/
H A Ddisplay-uclass.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <display.h>
16 if (!ops || !ops->read_edid) in display_read_edid()
17 return -ENOSYS; in display_read_edid()
18 return ops->read_edid(dev, buf, buf_size); in display_read_edid()
22 const struct display_timing *timing) in display_enable() argument
28 if (!ops || !ops->enable) in display_enable()
29 return -ENOSYS; in display_enable()
30 ret = ops->enable(dev, panel_bpp, timing); in display_enable()
35 disp_uc_plat->in_use = true; in display_enable()
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H A Dtegra.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/display.h>
21 #include <asm/arch-tegra/timer.h>
25 /* Information about the display controller */
30 struct display_timing timing; member
32 struct disp_ctlr *disp; /* Display controller to use */
49 val = readl(&dc->cmd.disp_win_header); in update_window()
51 writel(val, &dc->cmd.disp_win_header); in update_window()
53 writel(win->fmt, &dc->win.color_depth); in update_window()
55 clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, in update_window()
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H A Dihs_video_out.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <display.h>
74 /* Display width in text columns */
76 /* Display height in text rows */
78 /* x-resolution of the display in pixels */
80 /* y-resolution of the display in pixels */
84 /* The display port output for this OSD */
86 /* The pixel clock generator for the display */
96 * set_control() - Set the control register to a given value
101 * @value: the 16-bit value to write to the control register
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/openbmc/u-boot/drivers/video/rockchip/
H A Drk_vop.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <display.h>
21 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
41 u32 hactive = edid->hactive.typ; in rkvop_enable()
42 u32 vactive = edid->vactive.typ; in rkvop_enable()
44 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1), in rkvop_enable()
45 &regs->win0_act_info); in rkvop_enable()
47 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | in rkvop_enable()
48 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), in rkvop_enable()
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H A Drk_mipi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Eric Gao <eric.gao@rock-chips.com>
9 #include <display.h>
19 #include <dm/uclass-internal.h>
29 struct display_timing *timing) in rk_mipi_read_timing() argument
33 ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), in rk_mipi_read_timing()
34 0, timing); in rk_mipi_read_timing()
36 debug("%s: Failed to decode display timing (ret=%d)\n", in rk_mipi_read_timing()
38 return -EINVAL; in rk_mipi_read_timing()
61 mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); in rk_mipi_dsi_write()
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/openbmc/linux/Documentation/gpu/
H A Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
4 drm/komeda Arm display driver
7 The drm/komeda driver supports the Arm display processor D71 and later products,
11 Overview of D71 like display IPs
14 From D71, Arm display IP begins to adopt a flexible and modularized
15 architecture. A display pipeline is made up of multiple individual and
23 -----
30 ------
34 for layer scaling, or connected to compositor and scale the whole display
39 -------------------
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c45 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2; in dcn32_helper_mall_bytes_to_ways()
47 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; in dcn32_helper_mall_bytes_to_ways()
48 lines_per_way = total_cache_lines / dc->caps.cache_num_ways; in dcn32_helper_mall_bytes_to_ways()
61 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
62 uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; in dcn32_helper_calculate_mall_bytes_for_cursor()
65 switch (pipe_ctx->stream->cursor_attributes.color_format) { in dcn32_helper_calculate_mall_bytes_for_cursor()
84 if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf || in dcn32_helper_calculate_mall_bytes_for_cursor()
89 cursor_mall_size_bytes = ((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / in dcn32_helper_calculate_mall_bytes_for_cursor()
111 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
112 if (dc->debug.force_subvp_num_ways) { in dcn32_helper_calculate_num_ways_for_subvp()
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/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_lcd.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <display.h>
21 struct display_timing timing; member
49 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_lcd_enable()
51 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); in sunxi_lcd_enable()
55 lcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000, in sunxi_lcd_enable()
58 priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE); in sunxi_lcd_enable()
59 lcdc_enable(lcdc, priv->panel_bpp); in sunxi_lcd_enable()
69 struct display_timing *timing) in sunxi_lcd_read_timing() argument
73 memcpy(timing, &priv->timing, sizeof(struct display_timing)); in sunxi_lcd_read_timing()
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H A Dsunxi_de2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Allwinner DE2 display driver
9 #include <display.h>
20 #include <dm/device-internal.h>
21 #include <dm/uclass-internal.h>
50 clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, in sunxi_de2_composer_init()
54 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); in sunxi_de2_composer_init()
55 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); in sunxi_de2_composer_init()
58 setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); in sunxi_de2_composer_init()
81 u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ); in sunxi_de2_mode_set()
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/openbmc/linux/Documentation/fb/
H A Dmodedb.rst9 - one routine to probe for video modes, which can be used by all frame buffer
11 - one generic video mode database with a fair amount of standard videomodes
13 - the possibility to supply your own mode database for graphics hardware that
14 needs non-standard modes, like amifb and Mac frame buffer drivers (which
23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
24 <name>[-<bpp>][@<refresh>]
31 - NSTC: 480i output, with the CCIR System-M TV mode and NTSC color encoding
32 - NTSC-J: 480i output, with the CCIR System-M TV mode, the NTSC color
34 - PAL: 576i output, with the CCIR System-B TV mode and PAL color encoding
35 - PAL-M: 480i output, with the CCIR System-M TV mode and PAL color encoding
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/openbmc/linux/include/video/
H A Dvideomode.h1 /* SPDX-License-Identifier: GPL-2.0-only */
31 enum display_flags flags; /* display flags */
35 * videomode_from_timing - convert display timing to videomode
46 * videomode_from_timings - convert one display timings entry to videomode
47 * @disp: structure with all possible timing entries
49 * @index: index into the list of display timings in devicetree

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