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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Drockchip,iommu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
23 - rockchip,iommu
24 - rockchip,rk3568-iommu
28 - description: configuration registers for MMU instance 0
29 - description: configuration registers for MMU instance 1
34 - description: interruption for MMU instance 0
35 - description: interruption for MMU instance 1
[all …]
/openbmc/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
30 select GENERIC_STRNCPY_FROM_USER if MMU
31 select GENERIC_STRNLEN_USER if MMU
68 config MMU config
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
108 ISA for the Next Generation ARC-HS cores
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
[all …]
/openbmc/u-boot/arch/arm/cpu/arm1176/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for ARM1176 CPU-core
10 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
11 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
16 #include <asm-offsets.h>
27 * Startup Code (reset vector)
37 .globl reset
39 reset: label
64 * we do sys-critical inits only at reboot,
69 * When booting from NAND - it has definitely been a reset, so, no need
[all …]
/openbmc/linux/arch/xtensa/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_HAS_BINFMT_FLAT if !MMU
8 select ARCH_HAS_DMA_PREP_COHERENT if MMU
11 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
13 select ARCH_HAS_DMA_SET_UNCACHED if MMU
23 select DMA_NONCOHERENT_MMAP if MMU
31 select GENERIC_IOREMAP if MMU
34 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
58 Xtensa processors are 32-bit RISC machines designed by Tensilica
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * specification. Notice that while the IBM-40x series of CPUs
9 * Copyright 2009-2010 Freescale Semiconductor, Inc.
15 #include <asm/ppc-opcode.h>
19 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
26 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
75 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
78 #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
79 #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
85 #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
[all …]
/openbmc/linux/arch/arm64/kernel/
H A Dhyp-stub.S1 /* SPDX-License-Identifier: GPL-2.0-only */
35 ventry elx_sync // Synchronous 64-bit EL1
36 ventry el1_irq_invalid // IRQ 64-bit EL1
37 ventry el1_fiq_invalid // FIQ 64-bit EL1
38 ventry el1_error_invalid // Error 64-bit EL1
40 ventry el1_sync_invalid // Synchronous 32-bit EL1
41 ventry el1_irq_invalid // IRQ 32-bit EL1
42 ventry el1_fiq_invalid // FIQ 32-bit EL1
43 ventry el1_error_invalid // Error 32-bit EL1
66 beq 9f // Nothing to reset!
[all …]
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for XScale CPU-core
12 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
13 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
15 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
17 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
21 #include <asm-offsets.h>
27 * Startup Code (reset vector)
37 .globl reset
39 reset: label
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
7 #include <asm-offsets.h>
11 #include <asm/armv8/mmu.h>
15 * Startup Code (reset vector)
22 #include <asm/boot0-linux-kernel-header.h>
25 * Various SoCs need something special and SoC-specific up front in
31 b reset
45 .quad _end - _start
49 .quad __bss_start - _start
53 .quad __bss_end - _start
[all …]
/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
[all …]
/openbmc/linux/sound/pci/aw2/
H A Daw2-saa7146.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Jean-Christian Hassler <jhassler@free.fr>
24 #include "aw2-saa7146.h"
26 #include "aw2-tsl.c"
28 #define WRITEREG(value, addr) writel((value), chip->base_addr + (addr))
29 #define READREG(addr) readl(chip->base_addr + (addr))
38 /* chip-specific destructor */
41 /* disable all irqs */ in snd_aw2_saa7146_free()
44 /* reset saa7146 */ in snd_aw2_saa7146_free()
48 chip->base_addr = NULL; in snd_aw2_saa7146_free()
[all …]
/openbmc/linux/arch/arm/mm/
H A Dproc-sa110.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa110.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * MMU functions for SA110
11 * functions on the StrongARM-110.
17 #include <asm/asm-offsets.h>
20 #include <asm/pgtable-hwdef.h>
23 #include "proc-macros.S"
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
[all …]
H A Dproc-sa1100.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa1100.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * MMU functions for SA110
11 * functions on the StrongARM-1100 and StrongARM-1110.
15 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
22 #include <asm/asm-offsets.h>
25 #include <asm/pgtable-hwdef.h>
27 #include "proc-macros.S"
[all …]
H A Dproc-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v6.S
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
18 #include "proc-macros.S"
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 * Perform a soft reset of the system. Put the CPU into the
51 * same state as it would be if it had been reset, and branch
52 * to what would be the reset vector.
54 * - loc - location to jump to for soft reset
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Ddebugfs-driver-habanalabs46 the generic Linux user-space PCI mapping) because the DDR bar
61 the generic Linux user-space PCI mapping) because the DDR bar
77 Linux user-space PCI mapping) because the amount of internal
91 Valid values are "disable", "enable", "suspend", "resume".
99 certain error cases, after which the device is reset.
212 What: /sys/kernel/debug/habanalabs/hl<n>/mmu
220 echo "1 0x1000" > /sys/kernel/debug/habanalabs/hl0/mmu
226 Description: Check and display page fault or access violation mmu errors for
228 e.g. to display error info for MMU hw cap bit 9, you need to do:
241 Linux user-space PCI mapping) because this space is protected
[all …]
/openbmc/linux/Documentation/virt/kvm/arm/
H A Dhyp-abi.rst1 .. SPDX-License-Identifier: GPL-2.0
11 hypervisor), or any hypervisor-specific interaction when the kernel is
20 mode, but still needs to interact with it, allowing a built-in
28 Unless specified otherwise, any built-in hypervisor must implement
45 Turn HYP/EL2 MMU off, and reset HVBAR/VBAR_EL2 to the initials
57 Mask all exceptions, disable the MMU, clear I+D bits, move the arguments
65 Finish configuring EL2 depending on the command-line options,
68 supporting VHE, the EL2 MMU being off, and VHE not being disabled by
71 Any other value of r0/x0 triggers a hypervisor-specific handling,
76 clobber any of the caller-saved registers (x0-x18 on arm64, r0-r3 and
/openbmc/linux/arch/arm/mach-tegra/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
29 #include <asm/proc-fns.h>
36 #include "reset.h"
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
143 return -EBUSY; in tegra_sleep_cpu()
148 * MMU-on if cache maintenance is done via Trusted Foundations in tegra_sleep_cpu()
150 * if any of secondary CPU's is online and this is the LP2-idle in tegra_sleep_cpu()
151 * code-path only for Tegra20/30. in tegra_sleep_cpu()
154 if (trusted_foundations_registered() && outer_cache.disable) in tegra_sleep_cpu()
[all …]
H A Dsleep-tegra20.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
15 #include <asm/proc-fns.h>
20 #include "reset.h"
50 .arch armv7-a
89 * puts the current cpu in reset
102 * r0 is cpu to reset
104 * puts the specified CPU in wait-for-event mode on the flow controller
105 * and puts the CPU in reset
110 * corrupts r0-r3, r12
[all …]
/openbmc/linux/arch/riscv/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
23 select ARCH_HAS_DEBUG_VIRTUAL if MMU
35 select ARCH_HAS_SET_DIRECT_MAP if MMU
36 select ARCH_HAS_SET_MEMORY if MMU
37 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
38 select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL
48 select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU
49 select ARCH_SUPPORTS_HUGETLBFS if MMU
50 select ARCH_SUPPORTS_PAGE_TABLE_CHECK if MMU
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
119 * Start MMU after DDR is available, we create MMU table in DRAM.
120 * The base address of TTLB is gd->arch.tlb_addr. We use two
121 * levels of translation tables here to cover 40-bit address space.
127 * ------- <---- 0GB
130 * |-------| <---- 0x24000000
132 * |-------| <---- 0x300000000
134 * |-------| <---- 0x34000000
136 * |-------| <---- 0x40000000
138 * |-------| <---- 0x80000000 DDR0 space start
[all …]
/openbmc/linux/Documentation/powerpc/
H A Dbooting.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ------------------
9 bootloader <-> kernel interfaces, in order to avoid the degeneration that had
14 merged architecture for ppc32 and ppc64, new 32-bit platforms and 32-bit
19 of a device-tree whose format is defined after Open Firmware specification.
21 doesn't require the device-tree to represent every device in the system and only
47 bindings to powerpc. Only the 32-bit client interface
52 The MMU is either on or off; the kernel will run the
54 extract the device-tree and other information from open
55 firmware and build a flattened device-tree as described
[all …]
/openbmc/linux/drivers/accel/habanalabs/common/mmu/
H A Dmmu.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
15 * hl_mmu_get_funcs() - get MMU functions structure
20 * @return appropriate MMU functions structure
25 return &hdev->mmu_func[pgt_residency]; in hl_mmu_get_funcs()
30 struct asic_fixed_properties *prop = &hdev->asic_prop; in hl_is_dram_va()
32 return hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size, in hl_is_dram_va()
33 prop->dmmu.start_addr, in hl_is_dram_va()
34 prop->dmmu.end_addr); in hl_is_dram_va()
38 * hl_mmu_init() - initialize the MMU module.
[all …]
/openbmc/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2022 HabanaLabs, Ltd.
13 #include "../include/hw_ip/mmu/mmu_general.h"
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
42 * bits[63:59] - Encode mmap type
43 * bits[45:0] - mmap offset value
48 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
94 /* Default value for device reset trigger , an invalid value */
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
5 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
15 #include <asm-offsets.h>
23 * Startup Code (reset vector)
31 .globl reset
38 reset: label
45 * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
[all …]
/openbmc/u-boot/board/varisys/cyrus/
H A Dcyrus.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/mmu.h>
43 * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce in board_early_init_f()
46 setbits_be32(&gur->ddrclkdr, 0x001B001B); in board_early_init_f()
48 /* Set GPIO reset lines to open-drain, tristate */ in board_early_init_f()
49 setbits_be32(&pgpio->gpdat, GPIO_INITIAL); in board_early_init_f()
50 setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN); in board_early_init_f()
53 setbits_be32(&pgpio->gpdir, GPIO_DIR); in board_early_init_f()
62 out_be32(&lbc->lbcr, 0); in board_early_init_r()
64 out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR); in board_early_init_r()
/openbmc/u-boot/arch/arm/cpu/sa1100/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for SA1100 CPU
11 #include <asm-offsets.h>
17 * Startup Code (reset vector)
27 .globl reset
29 reset: label
39 * we do sys-critical inits only at reboot,
48 /*------------------------------------------------------------------------------*/
67 /* Interrupt-Controller base address */
72 /* Reset-Controller */
[all …]

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