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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd9576-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 powering the R-Car series processors.
21 - rohm,bd9576
22 - rohm,bd9573
32 rohm,vout1-en-low:
35 controlled by a GPIO. This is dictated by state of vout1-en pin during
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/openbmc/linux/drivers/regulator/
H A Dbd9571mwv-regulator.c1 // SPDX-License-Identifier: GPL-2.0
3 * ROHM BD9571MWV-M and BD9574MWF-M regulator driver
12 #include <linux/mfd/rohm-generic.h>
23 /* DDR Backup Power */
24 u8 bkup_mode_cnt_keepon; /* from "rohm,ddr-backup-power" */
57 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_SET_MONI, &val); in bd9571mwv_avs_get_moni_state()
65 unsigned int sel) in bd9571mwv_avs_set_voltage_sel_regmap() argument
73 return regmap_write_bits(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), in bd9571mwv_avs_set_voltage_sel_regmap()
74 rdev->desc->vsel_mask, sel); in bd9571mwv_avs_set_voltage_sel_regmap()
86 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), &val); in bd9571mwv_avs_get_voltage_sel_regmap()
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H A Dbd9576-regulator.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mfd/rohm-bd957x.h>
11 #include <linux/mfd/rohm-generic.h>
137 const struct regulator_desc *desc = rdev->desc; in bd957x_vout34_list_voltage()
138 int multiplier = selector & desc->vsel_mask & 0x7f; in bd957x_vout34_list_voltage()
145 return desc->fixed_uV - tune; in bd957x_vout34_list_voltage()
147 return desc->fixed_uV + tune; in bd957x_vout34_list_voltage()
153 const struct regulator_desc *desc = rdev->desc; in bd957x_list_voltage()
154 int index = selector & desc->vsel_mask & 0x7f; in bd957x_list_voltage()
157 index += desc->n_voltages/2; in bd957x_list_voltage()
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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/openbmc/qemu/hw/arm/
H A Dxlnx-versal.c24 #include "hw/arm/xlnx-versal.h"
26 #include "target/arm/cpu-qom.h"
29 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
30 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
40 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, in versal_create_apu_cpus()
42 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); in versal_create_apu_cpus()
44 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { in versal_create_apu_cpus()
47 object_initialize_child(OBJECT(&s->fpd.apu.cluster), in versal_create_apu_cpus()
48 "apu-cpu[*]", &s->fpd.apu.cpu[i], in versal_create_apu_cpus()
50 obj = OBJECT(&s->fpd.apu.cpu[i]); in versal_create_apu_cpus()
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/openbmc/u-boot/drivers/power/regulator/
H A Dstpmu1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
44 static int stpmu1_output_find_uv(int sel, in stpmu1_output_find_uv() argument
50 for (i = 0, range = output_range->ranges; in stpmu1_output_find_uv()
51 i < output_range->nbranges; i++, range++) { in stpmu1_output_find_uv()
52 if (sel >= range->min_sel && sel <= range->max_sel) in stpmu1_output_find_uv()
53 return range->min_uv + in stpmu1_output_find_uv()
54 (sel - range->min_sel) * range->step; in stpmu1_output_find_uv()
57 return -EINVAL; in stpmu1_output_find_uv()
66 for (i = 0, range = output_range->ranges; in stpmu1_output_find_sel()
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-ampere-mtjade.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
12 * i2c bus 50-57 assigned to NVMe slot 0-7
24 * i2c bus 60-67 assigned to NVMe slot 8-15
36 * i2c bus 70-77 assigned to NVMe slot 16-23
48 * i2c bus 80-81 assigned to NVMe M2 slot 0-1
60 stdout-path = &uart5;
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H A Daspeed-bmc-ampere-mtjefferson.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/gpio/aspeed-gpio.h>
12 compatible = "ampere,mtjefferson-bmc", "aspeed,ast2600";
41 stdout-path = &uart5;
49 reserved-memory {
50 #address-cells = <1>;
51 #size-cells = <1>;
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H A Daspeed-bmc-ampere-mtmitchell.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/gpio/aspeed-gpio.h>
12 compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
27 * i2c bus 30-31 assigned to OCP slot 0-1
33 * i2c bus 32-33 assigned to Riser slot 0-1
39 * i2c bus 38-39 assigned to FRU on Riser slot 0-1
82 stdout-path = &uart5;
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/openbmc/u-boot/board/hisilicon/hikey/
H A DREADME4 HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
5 * HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
6 * ARM Mali 450-MP4 GPU
12 The HiKey schematic can be found here: -
13 https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_s…
15 The SoC datasheet can be found here: -
16 …boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Appli…
18 Currently the u-boot port supports: -
24 The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
25 U-Boot as the bl33.bin executable.
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/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Datomisp_v4l2.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
30 #include <media/v4l2-fwnode.h>
41 #include "atomisp-regs.h"
55 /* G-Min addition: pull this in from intel_mid_pm.h */
341 video->pad.flags = MEDIA_PAD_FL_SINK; in atomisp_video_init()
342 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad); in atomisp_video_init()
347 strscpy(video->vdev.name, "ATOMISP video output", sizeof(video->vdev.name)); in atomisp_video_init()
348 video->vdev.fops = &atomisp_fops; in atomisp_video_init()
349 video->vdev.ioctl_ops = &atomisp_ioctl_ops; in atomisp_video_init()
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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 atf-sram@0 {
20 tifs-sram@1f0000 {
24 l3cache-sram@200000 {
29 gic500: interrupt-controller@1800000 {
30 compatible = "arm,gic-v3";
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H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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/openbmc/openbmc/meta-ampere/meta-common/recipes-ampere/host/ac01-boot-progress/
H A Ddimm_train_fail_log.sh4 echo "/sys/bus/i2c/drivers/smpro-core/2-004f"
6 echo "/sys/bus/i2c/drivers/smpro-core/2-004e"
19 logger --journald << EOF
112 #smg=$("DDR training: MCU rank $rank: $fType: $redfisMsg")
132 # sel type: 4 byte [0x00 0x00 0x00 0xC0]
158 path=("$base"/smpro-misc.*.auto/boot_progress)
160 if [ ! -f "$filename" ];
171 # Checking for DIMM slot 0-15
174 path=("$base"/smpro-errmon.*.auto/event_dimm"${i}"_syndrome)
176 if [ ! -f "$filename" ];
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/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
380 u8 sel; member
406 const struct stm32mp1_clk_sel *sel; member
424 .sel = (s), \
434 .sel = _UNKNOWN_SEL, \
444 .sel = (s), \
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/openbmc/pldm/oem/ampere/event/
H A Doem_event_manager.hpp8 #include "platform-mc/manager.hpp"
86 * Bit 30:24 | Media slot number (0 - 63) This field can be used by UEFI
91 * Bit 22 | Action: 0 - Insertion 1 - Removal
131 namespace ddr namespace
146 } // namespace ddr
209 * Bit 15:8 | VR status byte high - The bit definition is the same as the
211 * Bit 7:0 | VR status byte low - The bit definition is the same as the
252 * @param[in] request - the request message of sensor event
253 * @param[in] payloadLength - the payload length of sensor event
254 * @param[in] formatVersion - the format version of sensor event
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H A Doem_event_manager.cpp12 #include <systemd/sd-journal.h>
14 #include <phosphor-logging/lg2.hpp>
32 namespace ddr_status = ddr::status;
55 An array of possible boot status of DDR training stage.
59 " progress started", " in-progress", " progress completed"};
107 {boot_stage::DDR_INITIALIZATION, "DDR initialization"},
108 {boot_stage::DDR_TRAINING, "DDR training"},
109 {boot_stage::S0_DDR_TRAINING_FAILURE, "DDR training failure"},
112 {boot_stage::S1_DDR_TRAINING_FAILURE, "DDR training failure"},
117 A map between DDR status and logging strings.
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/openbmc/linux/drivers/mtd/nand/raw/
H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-phycore-stm32mp15-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2022-2023 Steffen Trumtrar <kernel@pengutronix.de>
4 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/leds/leds-pca9532.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
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/openbmc/linux/drivers/perf/
H A Dalibaba_uncore_drw_pmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Alibaba DDR Sub-System Driveway PMU driver
55 /* PMU EVENT SEL 0-3 are paired in 32-bit registers on a 4-byte stride */
57 /* counter 0-3 use sel0, counter 4-7 use sel1...*/
65 /* PMU COMMON COUNTER 0-15, are paired in 32-bit registers on a 4-byte stride */
111 #define GET_DRW_EVENTID(event) FIELD_GET(DRW_CONFIG_EVENTID, (event)->attr.config)
120 return sprintf(buf, "%s\n", (char *)eattr->var); in ali_drw_pmu_format_show()
133 return sprintf(page, "config=0x%lx\n", (unsigned long)eattr->var); in ali_drw_pmu_event_show()
209 ALI_DRW_PMU_FORMAT_ATTR(event, "config:0-7"),
224 return cpumap_print_to_pagebuf(true, buf, cpumask_of(drw_pmu->cpu)); in ali_drw_pmu_cpumask_show()
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