Home
last modified time | relevance | path

Searched +full:dc +full:- +full:dc +full:- +full:phase (Results 1 – 25 of 120) sorted by relevance

12345

/openbmc/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad5755.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.c35 (dccg_dcn->regs->reg)
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
42 dccg_dcn->base.ctx
44 dccg->ctx->logger
50 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
58 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
59 int ref_dppclk = dccg->ref_dppclk; in dccg31_update_dpp_dto()
60 int modulo, phase; in dccg31_update_dpp_dto() local
62 // phase / modulo = dpp pipe clk / dpp global clk in dccg31_update_dpp_dto()
64 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg31_update_dpp_dto()
[all …]
/openbmc/qemu/hw/core/
H A Dqdev.c30 #include "qapi/qapi-events-qdev.h"
33 #include "qemu/error-report.h"
36 #include "hw/qdev-properties.h"
39 #include "hw/qdev-clock.h"
48 DeviceClass *dc = DEVICE_GET_CLASS(dev); in qdev_get_vmsd() local
49 return dc->vmsd; in qdev_get_vmsd()
54 object_unref(OBJECT(kid->child)); in bus_free_bus_child()
62 QTAILQ_FOREACH(kid, &bus->children, sibling) { in bus_remove_child()
63 if (kid->child == child) { in bus_remove_child()
66 snprintf(name, sizeof(name), "child[%d]", kid->index); in bus_remove_child()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c2 * Copyright 2020-2021 Advanced Micro Devices, Inc.
37 optc1->tg_regs->reg
40 optc1->base.ctx
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
186 double ratio, modulo, phase; in optc3_fpu_set_vrr_m_const() local
193 * VOTAL_MAX - VTOTAL_MIN = 1 in optc3_fpu_set_vrr_m_const()
201 * of lines in a frame - 1'. in optc3_fpu_set_vrr_m_const()
213 optc->funcs->set_vtotal_min_max(optc, 0, 0); in optc3_fpu_set_vrr_m_const()
223 ratio = vtotal_max - vtotal_avg; in optc3_fpu_set_vrr_m_const()
224 modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */ in optc3_fpu_set_vrr_m_const()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
31 - enum:
33 - acbel,fsg032
34 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
35 - ad,ad7414
[all …]
/openbmc/linux/drivers/regulator/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
65 They provide two I2C-controlled DC/DC step-down converters with
85 tristate "Active-semi act8865 voltage regulator"
90 This driver controls a active-semi act8865 voltage output
94 tristate "Active-semi ACT8945A voltage regulator"
97 This driver controls a active-semi ACT8945A voltage regulator
98 via I2C bus. The ACT8945A features three step-down DC/DC converters
99 and four low-dropout linear regulators, along with a ActivePath
110 tristate "Freescale i.MX on-chip ANATOP LDO regulators"
[all …]
/openbmc/linux/drivers/tty/
H A Dnozomi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
78 if (tbuf[data_len - 2] == '\r') \
79 tbuf[data_len - 2] = 'r'; \
148 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
149 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
173 CTRL_ERROR = -1,
183 PORT_ERROR = -1,
[all …]
/openbmc/qemu/hw/pci-host/
H A Dversatile.c4 * Copyright (c) 2006-2009 CodeSourcery.
18 #include "hw/qdev-properties.h"
41 * phase I (before kernel commit 1bc39ac5d) kernels assume old
43 * phase II (1bc39ac5d and later, but before e3e92a7be6) kernels
48 * phase III (e3e92a7be6 and later) kernels still swizzle IRQs between
52 * We live in hope of a mythical phase IV kernel which might
59 * -------------------------------
116 if (s->realview) { in pci_vpb_update_window()
120 offset = s->imap[i] & ~(s->mem_win_size[i] - 1); in pci_vpb_update_window()
123 offset = s->imap[i] << 28; in pci_vpb_update_window()
[all …]
/openbmc/qemu/hw/audio/
H A Dasc.c7 * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
8 * Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
10 * SPDX-License-Identifier: GPL-2.0-or-later
19 #include "hw/qdev-properties.h"
44 * bit 1="non-ROM companding",
52 * bits 0-3 wavetables 0-3 start
54 * bits 2-4 = 3 bit internal ASC volume,
55 * bits 5-7 = volume control sent to Sony sound chip
63 * bits 6-7 = digital test,
64 * bits 4-5 = analog test
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_dscl.c44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
65 /* Autocal calculate the scaling ratio and initial phase and the
101 return -1; /* Unsupported */ in dpp1_dscl_get_pixel_depth_val()
130 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
132 if (data->format == PIXEL_FORMAT_FP16) in dpp1_dscl_get_dscl_mode()
136 if (data->ratios.horz.value == one in dpp1_dscl_get_dscl_mode()
137 && data->ratios.vert.value == one in dpp1_dscl_get_dscl_mode()
138 && data->ratios.horz_c.value == one in dpp1_dscl_get_dscl_mode()
[all …]
H A Ddcn10_hw_sequencer.c63 hws->ctx
65 hws->regs->reg
69 hws->shifts->field_name, hws->masks->field_name
84 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
93 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
102 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
103 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
104 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
105 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
111 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.c1 // SPDX-License-Identifier: MIT
37 (dccg_dcn->regs->reg)
41 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
44 dccg_dcn->base.ctx
46 dccg->ctx->logger
203 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
210 int req_dtbclk_khz = params->pixclk_khz / 4; in dccg314_set_dtbclk_dto()
212 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg314_set_dtbclk_dto()
213 uint32_t modulo, phase; in dccg314_set_dtbclk_dto() local
215 // phase / modulo = dtbclk / dtbclk ref in dccg314_set_dtbclk_dto()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dsolomon,ssd1307fb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
[all …]
/openbmc/linux/drivers/iio/dac/
H A Dad5755.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
128 * struct ad5755_platform_data - AD5755 DAC driver platform data
129 * @ext_dc_dc_compenstation_resistor: Whether an external DC-DC converter
131 * @dc_dc_phase: DC-DC converter phase.
132 * @dc_dc_freq: DC-DC converter frequency.
133 * @dc_dc_maxv: DC-DC maximum allowed boost voltage.
162 * struct ad5755_chip_info - chip specific information
174 * struct ad5755_state - driver instance specific data
257 st->data[0].d32 = cpu_to_be32((reg << 16) | val); in ad5755_write_unlocked()
[all …]
/openbmc/linux/Documentation/hwmon/
H A Ducd9200.rst11 Addresses scanned: -
15 - http://focus.ti.com/lit/ds/symlink/ucd9220.pdf
16 - http://focus.ti.com/lit/ds/symlink/ucd9222.pdf
17 - http://focus.ti.com/lit/ds/symlink/ucd9224.pdf
18 - http://focus.ti.com/lit/ds/symlink/ucd9240.pdf
19 - http://focus.ti.com/lit/ds/symlink/ucd9244.pdf
20 - http://focus.ti.com/lit/ds/symlink/ucd9246.pdf
21 - http://focus.ti.com/lit/ds/symlink/ucd9248.pdf
23 Author: Guenter Roeck <linux@roeck-us.net>
27 -----------
[all …]
H A Dxdpe12284.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -----------
27 This driver implements support for Infineon Multi-phase XDPE112 and XDPE122
32 - Intel VR13 and VR13HC rev 1.3, IMVP8 rev 1.2 and IMPVP9 rev 1.3 DC-DC
34 - Intel SVID rev 1.9. protocol.
35 - PMBus rev 1.3 interface.
41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
[all …]
H A Dltc2978.rst10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 Addresses scanned: -
42 Addresses scanned: -
52 Addresses scanned: -
60 Addresses scanned: -
68 Addresses scanned: -
76 Addresses scanned: -
84 Addresses scanned: -
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DCircuit_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: Circuit v1.8.1 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
/openbmc/qemu/hw/scsi/
H A Desp.c4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Copyright (c) 2023 Mark Cave-Ayland
39 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
48 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { in esp_raise_irq()
49 s->rregs[ESP_RSTAT] |= STAT_INT; in esp_raise_irq()
50 qemu_irq_raise(s->irq); in esp_raise_irq()
57 if (s->rregs[ESP_RSTAT] & STAT_INT) { in esp_lower_irq()
58 s->rregs[ESP_RSTAT] &= ~STAT_INT; in esp_lower_irq()
59 qemu_irq_lower(s->irq); in esp_lower_irq()
[all …]
/openbmc/linux/drivers/hwmon/pmbus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
37 be called acbel-fsg032.
55 and ADM1294 Hot-Swap Controller and Digital Power Monitors.
67 be called bel-pfe.
70 tristate "BluTek BPA-RS600 Power Supplies"
73 BPA-RS600 Power Supplies.
76 be called bpa-rs600.
88 tristate "Delta AHE-50DC fan control module"
91 the integrated fan control module of the Delta AHE-50DC
95 will be called delta-ahe50dc-fan.
[all …]
H A Ddelta-ahe50dc-fan.c1 // SPDX-License-Identifier: GPL-2.0
3 * Delta AHE-50DC power shelf fan control module driver
29 return value == PMBUS_CLEAR_FAULTS ? -EOPNOTSUPP : -ENODATA; in ahe50dc_fan_write_byte()
32 static int ahe50dc_fan_read_word_data(struct i2c_client *client, int page, int phase, int reg) in ahe50dc_fan_read_word_data() argument
34 /* temp1 in (virtual) page 1 is remapped to mfr-specific temp4 */ in ahe50dc_fan_read_word_data()
38 return -EOPNOTSUPP; in ahe50dc_fan_read_word_data()
62 return -ENODATA; in ahe50dc_fan_read_word_data()
64 return -EOPNOTSUPP; in ahe50dc_fan_read_word_data()
101 client->dev.platform_data = &ahe50dc_fan_data; in ahe50dc_fan_probe()
112 { .compatible = "delta,ahe50dc-fan" },
[all …]
/openbmc/qemu/hw/m68k/
H A Dnext-cube.c17 #include "hw/m68k/next-cube.h"
25 #include "hw/qdev-properties.h"
27 #include "qemu/error-report.h"
40 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
65 int8_t phase; member
86 #define TYPE_NEXT_PC "next-pc"
135 if (s->scr2 & 0x1) { in next_scr2_led_update()
137 s->led++; in next_scr2_led_update()
138 if (s->led == 10) { in next_scr2_led_update()
140 s->led = 0; in next_scr2_led_update()
[all …]
/openbmc/qemu/include/hw/
H A Dqdev-core.h22 * -----------
31 * information to the caller and must be re-entrant.
57 * ---------------
62 * DeviceListener can save the QOpts passed to it for re-using it
73 DEV_NVECTORS_UNSPECIFIED = -1,
101 * struct DeviceClass - The base class for all devices.
107 * @sync_config: Callback function invoked when QMP command device-sync-config
136 * ensures a compile-time error if someone attempts to assign
137 * dc->props directly.
142 * @user_creatable: Can user instantiate with -device / device_add?
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
53 int modulo, phase; in dccg2_update_dpp_dto() local
55 // phase / modulo = dpp pipe clk / dpp global clk in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
59 if (phase > 0xff) { in dccg2_update_dpp_dto()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
41 (clk_src->regs->reg)
44 clk_src->base.ctx
50 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
72 ss_parm = clk_src->dvi_ss_params; in get_ss_data_entry()
73 entrys_num = clk_src->dvi_ss_params_cnt; in get_ss_data_entry()
77 ss_parm = clk_src->hdmi_ss_params; in get_ss_data_entry()
78 entrys_num = clk_src->hdmi_ss_params_cnt; in get_ss_data_entry()
82 ss_parm = clk_src->lvds_ss_params; in get_ss_data_entry()
83 entrys_num = clk_src->lvds_ss_params_cnt; in get_ss_data_entry()
[all …]

12345