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/openbmc/qemu/target/ppc/
H A Dmmu_helper.c2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
25 #include "mmu-hash64.h"
26 #include "mmu-hash32.h"
27 #include "exec/exec-all.h"
28 #include "exec/page-protection.h"
31 #include "qemu/error-report.h"
32 #include "qemu/qemu-print.h"
34 #include "mmu-book3s-v3.h"
35 #include "mmu-radix64.h"
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H A Dmmu_common.c2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
25 #include "mmu-hash64.h"
26 #include "mmu-hash32.h"
27 #include "exec/exec-all.h"
28 #include "exec/page-protection.h"
31 #include "qemu/error-report.h"
32 #include "qemu/qemu-print.h"
34 #include "mmu-book3s-v3.h"
35 #include "mmu-radix64.h"
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/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/openbmc/linux/arch/loongarch/mm/
H A Dtlbex.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
14 #define PTRS_PER_PGD_BITS (PAGE_SHIFT - 3)
15 #define PTRS_PER_PUD_BITS (PAGE_SHIFT - 3)
16 #define PTRS_PER_PMD_BITS (PAGE_SHIFT - 3)
17 #define PTRS_PER_PTE_BITS (PAGE_SHIFT - 3)
60 bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
61 alsl.d t1, ra, t1, 3
63 ld.d t1, t1, 0
64 bstrpick.d ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
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/openbmc/qemu/accel/tcg/
H A Dcputlb.c2 * Common CPU TLB handling
21 #include "qemu/main-loop.h"
22 #include "hw/core/tcg-cpu-ops.h"
23 #include "exec/exec-all.h"
24 #include "exec/page-protection.h"
28 #include "exec/tb-flush.h"
29 #include "exec/memory-internal.h"
31 #include "exec/mmu-access-type.h"
32 #include "exec/tlb-common.h"
35 #include "qemu/error-report.h"
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/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
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/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/openbmc/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
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/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/openbmc/linux/Documentation/core-api/
H A Dcachetlb.rst2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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/openbmc/linux/arch/parisc/kernel/
H A Dcache.c6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10 * Cache and TLB management
55 void flush_data_cache_local(void *); /* flushes local data-cache only */
56 void flush_instruction_cache_local(void); /* flushes local code-cache only */
62 * by software. We need a spinlock around all TLB flushes to ensure
125 test_bit(PG_dcache_dirty, &folio->flags)) { in __update_cache()
126 while (nr--) in __update_cache()
128 clear_bit(PG_dcache_dirty, &folio->flags); in __update_cache()
130 while (nr--) in __update_cache()
139 seq_printf(m, "I-cache\t\t: %ld KB\n", in show_cache_info()
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
20 void invalidate_tlb(u8 tlb) in invalidate_tlb() argument
22 if (tlb == 0) in invalidate_tlb()
24 if (tlb == 1) in invalidate_tlb()
76 printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:", in print_tlbcam()
88 gd->arch.used_tlb_cams[i] |= (1 << bit); in use_tlb_cam()
96 gd->arch.used_tlb_cams[i] &= ~(1 << bit); in free_tlb_cam()
105 gd->arch.used_tlb_cams[i] = 0; in init_used_tlb_cams()
122 idx = ffz(gd->arch.used_tlb_cams[i]); in find_free_tlbcam()
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/openbmc/u-boot/doc/
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
9 - 8-stage pipeline.
10 - Dynamic branch prediction.
11 - 32/64/128/256 BTB.
12 - Return address stack (RAS).
13 - Vector interrupts for internal/external.
15 - 3 HW-level nested interruptions.
16 - User and super-user mode support.
17 - Memory-mapped I/O.
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/openbmc/qemu/target/sparc/
H A Dldst_helper.c4 * Copyright (c) 2003-2005 Fabrice Bellard
25 #include "exec/helper-proto.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
65 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
72 /* Calculates TSB pointer value for fault page size
74 * UA2005 holds the page size configuration in mmu_ctx registers */
82 int ctx = mmu->tag_access & 0x1fffULL; in ultrasparc_tsb_pointer()
83 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; in ultrasparc_tsb_pointer()
88 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; in ultrasparc_tsb_pointer()
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/openbmc/linux/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
63 /* Locate the TLB entry for this vaddr + ASID */ in tlb_entry_erase()
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
95 /* setup the other half of TLB entry (pfn, rwx..) */ in tlb_entry_insert()
101 * which doesn't flush uTLBs. I'd rather be safe than sorry. in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
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/openbmc/linux/include/asm-generic/
H A Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_gather_mmu_fullmm() / tlb_finish_mmu()
53 * Finish in particular will issue a (final) TLB invalidate and free
56 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
61 * - tlb_remove_table()
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/openbmc/qemu/target/sh4/
H A Dmonitor.c4 * Copyright (c) 2003-2004 Fabrice Bellard
27 #include "monitor/hmp-target.h"
30 static void print_tlb(Monitor *mon, int idx, tlb_t *tlb) in print_tlb() argument
32 monitor_printf(mon, " tlb%i:\t" in print_tlb()
33 "asid=%hhu vpn=%x\tppn=%x\tsz=%hhu size=%u\t" in print_tlb()
37 tlb->asid, tlb->vpn, tlb->ppn, tlb->sz, tlb->size, in print_tlb()
38 tlb->v, tlb->sh, tlb->c, tlb->pr, in print_tlb()
39 tlb->d, tlb->wt); in print_tlb()
54 print_tlb (mon, i, &env->itlb[i]); in hmp_info_tlb()
57 print_tlb (mon, i, &env->utlb[i]); in hmp_info_tlb()
/openbmc/qemu/target/hppa/
H A Dmachine.c25 static int get_psw(QEMUFile *f, void *opaque, size_t size, in get_psw() argument
33 static int put_psw(QEMUFile *f, void *opaque, size_t size, in put_psw() argument
47 static int get_tlb(QEMUFile *f, void *opaque, size_t size, in get_tlb() argument
53 ent->itree.start = qemu_get_be64(f); in get_tlb()
54 ent->itree.last = qemu_get_be64(f); in get_tlb()
55 ent->pa = qemu_get_be64(f); in get_tlb()
59 ent->t = extract64(val, 61, 1); in get_tlb()
60 ent->d = extract64(val, 60, 1); in get_tlb()
61 ent->b = extract64(val, 59, 1); in get_tlb()
62 ent->ar_type = extract64(val, 56, 3); in get_tlb()
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H A Dmem_helper.c23 #include "exec/exec-all.h"
24 #include "exec/page-protection.h"
25 #include "exec/helper-proto.h"
32 * Figure H-8 "62-bit Absolute Accesses when PSW W-bit is 1" describes in hppa_abs_to_phys_pa2_w1()
33 * an algorithm in which a 62-bit absolute address is transformed to in hppa_abs_to_phys_pa2_w1()
34 * a 64-bit physical address. This must then be combined with that in hppa_abs_to_phys_pa2_w1()
35 * pictured in Figure H-11 "Physical Address Space Mapping", in which in hppa_abs_to_phys_pa2_w1()
36 * the full physical address is truncated to the N-bit physical address in hppa_abs_to_phys_pa2_w1()
40 * H-8 algorithm is moot and all that is left is to truncate. in hppa_abs_to_phys_pa2_w1()
49 * See Figure H-10, "Absolute Accesses when PSW W-bit is 0", in hppa_abs_to_phys_pa2_w0()
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/openbmc/linux/arch/parisc/include/uapi/asm/
H A Dpdc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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/openbmc/linux/Documentation/arch/loongarch/
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
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/openbmc/linux/drivers/parisc/
H A Dccio-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
9 ** (c) Copyright 2000 Hewlett-Packard Company
13 ** the I/O MMU - basically what x86 does.
16 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
17 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
19 ** o Doesn't work under PCX-U/U+ machines since they didn't follow
20 ** the coherency design originally worked out. Only PCX-W does.
34 #include <linux/dma-map-ops.h>
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/openbmc/qemu/target/loongarch/tcg/
H A Dtlb_helper.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QEMU LoongArch TLB helpers
10 #include "qemu/guest-random.h"
14 #include "exec/helper-proto.h"
15 #include "exec/exec-all.h"
16 #include "exec/page-protection.h"
19 #include "cpu-csr.h"
26 *dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_BASE); in get_dir_base_width()
27 *dir_width = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_WIDTH); in get_dir_base_width()
30 *dir_base = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR2_BASE); in get_dir_base_width()
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