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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)2 /* Copyright (c) 2018-2019 SiFive, Inc */4 /dts-v1/;6 #include <dt-bindings/clock/sifive-fu540-prci.h>9 #address-cells = <2>;10 #size-cells = <2>;11 compatible = "sifive,fu540-c000", "sifive,fu540";23 #address-cells = <1>;24 #size-cells = <0>;28 i-cache-block-size = <64>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)4 /dts-v1/;6 #include <dt-bindings/clock/sifive-fu740-prci.h>9 #address-cells = <2>;10 #size-cells = <2>;11 compatible = "sifive,fu740-c000", "sifive,fu740";23 #address-cells = <1>;24 #size-cells = <0>;28 i-cache-block-size = <64>;29 i-cache-sets = <128>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)7 #include <dt-bindings/interrupt-controller/irq.h>11 #address-cells = <2>;12 #size-cells = <2>;15 #address-cells = <1>;16 #size-cells = <0>;17 timebase-frequency = <3000000>;24 i-cache-block-size = <64>;25 i-cache-size = <65536>;26 i-cache-sets = <512>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V CPUs10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 This document uses some terminology common to the RISC-V community19 mandated by the RISC-V ISA: a PC and some registers. This27 - $ref: /schemas/cpu.yaml#[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)2 /* Copyright (c) 2020-2021 Microchip Technology Inc */4 /dts-v1/;5 #include "dt-bindings/clock/microchip,mpfs-clock.h"8 #address-cells = <2>;9 #size-cells = <2>;14 #address-cells = <1>;15 #size-cells = <0>;20 i-cache-block-size = <64>;21 i-cache-sets = <128>;[all …]
2 A block layer cache (bcache)6 nice if you could use them as cache... Hence bcache.11 This is the git repository of bcache-tools:12 https://git.kernel.org/pub/scm/linux/kernel/git/colyli/bcache-tools.git/17 It's designed around the performance characteristics of SSDs - it only allocates18 in erase block sized buckets, and it uses a hybrid btree/log to track cached19 extents (which can be anywhere from a single sector to the bucket size). It's20 designed to avoid random writes at all costs; it fills up an erase block25 great lengths to protect your data - it reliably handles unclean shutdown. (It29 Writeback caching can use most of the cache for buffering writes - writing[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Squashfs - a compressed read only filesystem for Linux14 * compressed fragment block (tail-end packed block). The compressed size15 * of each datablock is stored in a block list contained within the19 * larger), the code implements an index cache that caches the mapping from20 * block index to datablock location on disk.22 * The index cache allows Squashfs to handle large files (up to 1.75 TiB) while23 * retaining a simple and space-efficient block list on disk. The cache26 * The index cache is designed to be memory efficient, and by default uses45 * Locate cache slot in range [offset, index] for specified inode. If[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Processor cache information made available to userspace via sysfs;26 /* per-cpu object for tracking:27 * - a "cache" kobject for the top-level directory28 * - a list of "index" objects representing the cpu's local cache hierarchy31 struct kobject *kobj; /* bare (not embedded) kobject for cache36 /* "index" object: each cpu's cache directory has an index37 * subdirectory corresponding to a cache object associated with the43 struct cache *cache; member47 * cache type */[all …]
21 #include "exec/page-vary.h"31 #include "hw/core/tcg-cpu-ops.h"34 #include "exec/exec-all.h"35 #include "exec/page-protection.h"37 #include "hw/qdev-core.h"38 #include "hw/qdev-properties.h"45 #include "qemu/config-file.h"46 #include "qemu/error-report.h"47 #include "qemu/qemu-print.h"55 #include "sysemu/xen-mapcache.h"[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */62 __u64 physicalMemorySize; /* Size of real memory(B) 0x28 */70 __u32 dcache_size; /* L1 d-cache size 0x60 */71 __u32 dcache_line_size; /* L1 d-cache line size 0x64 */72 __u32 icache_size; /* L1 i-cache size 0x68 */73 __u32 icache_line_size; /* L1 i-cache line size 0x6C */78 __u32 dcache_block_size; /* L1 d-cache block size */79 __u32 icache_block_size; /* L1 i-cache block size */80 __u32 dcache_log_block_size; /* L1 d-cache log block size */81 __u32 icache_log_block_size; /* L1 i-cache log block size */[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2001-2003 Andreas Gruenbacher <agruen@suse.de>18 * block. If all extended attributes of an inode are identical, these19 * inodes may share the same extended attribute block. Such situations20 * are automatically detected by keeping a cache of recent attribute block21 * numbers and hashes over the block's contents in memory.24 * Extended attribute block layout:26 * +------------------+36 * +------------------+38 * The block header is followed by multiple entry descriptors. These entry[all …]
1 // SPDX-License-Identifier: GPL-2.05 * (c) 1996 Hans-Joachim Widmaier - Rewritten7 * (C) 1993 Ray Burr - Modified for Amiga FFS filesystem.11 * (C) 1991 Linus Torvalds - minix filesystem26 pr_debug("open(%lu,%d)\n", in affs_file_open()27 inode->i_ino, atomic_read(&AFFS_I(inode)->i_opencnt)); in affs_file_open()28 atomic_inc(&AFFS_I(inode)->i_opencnt); in affs_file_open()35 pr_debug("release(%lu, %d)\n", in affs_file_release()36 inode->i_ino, atomic_read(&AFFS_I(inode)->i_opencnt)); in affs_file_release()38 if (atomic_dec_and_test(&AFFS_I(inode)->i_opencnt)) { in affs_file_release()[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR MIT7 /dts-v1/;8 #include <dt-bindings/clock/starfive-jh7100.h>9 #include <dt-bindings/reset/starfive-jh7100.h>13 #address-cells = <2>;14 #size-cells = <2>;17 #address-cells = <1>;18 #size-cells = <0>;21 compatible = "sifive,u74-mc", "riscv";23 d-cache-block-size = <64>;[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR MIT7 /dts-v1/;8 #include <dt-bindings/clock/starfive,jh7110-crg.h>9 #include <dt-bindings/power/starfive,jh7110-pmu.h>10 #include <dt-bindings/reset/starfive,jh7110-crg.h>11 #include <dt-bindings/thermal/thermal.h>15 #address-cells = <2>;16 #size-cells = <2>;19 #address-cells = <1>;20 #size-cells = <0>;[all …]
15 /dts-v1/;20 #address-cells = <2>;21 #size-cells = <1>;22 model = "ibm,iss-4xx";23 compatible = "ibm,iss-4xx";24 dcr-parent = <&{/cpus/cpu@0}>;31 #address-cells = <1>;32 #size-cells = <0>;38 clock-frequency = <100000000>; // 100Mhz :-)39 timebase-frequency = <100000000>;[all …]
1 /dts-v1/;4 #size-cells = <0x02>;5 #address-cells = <0x02>;6 model-name = "microwatt";7 compatible = "microwatt-soc";13 reserved-memory {14 #size-cells = <0x02>;15 #address-cells = <0x02>;26 #clock-cells = <0>;27 compatible = "fixed-clock";[all …]
1 // SPDX-License-Identifier: GPL-2.0+26 * 63-48 47-39 38-30 29-21 20-12 11-0028 * mask page size30 * Lv0: FF8000000000 --45 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) in get_tcr()46 max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size); in get_tcr()100 return (12 + 9 * (3 - level)); in level2shift()111 debug("addr=%llx level=%d\n", addr, level); in find_pte()121 pte = (u64*)gd->arch.tlb_addr; in find_pte()125 debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte); in find_pte()[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>6 #include "sunxi-d1s-t113.dtsi"10 timebase-frequency = <24000000>;11 #address-cells = <1>;12 #size-cells = <0>;19 d-cache-block-size = <64>;20 d-cache-sets = <256>;21 d-cache-size = <32768>;22 i-cache-block-size = <64>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README5 * GRUB -- GRand Unified Bootloader8 * (C) Copyright 2003 - 200451 return -1; in substring()66 printf ("%-10s %4hd %6d %6d %9d %24.24s", in sd_print_item()73 printf ("%-10s %4d %6d %6d %9d %24.24s", in sd_print_item()80 journal_read (int block, int len, char *buffer) in journal_read() argument82 return reiserfs_devread ((INFO->journal_block + block) << INFO->blocksize_shift, in journal_read()86 /* Read a block from ReiserFS file system, taking the journal into[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;5 compatible = "jcore,j2-soc";8 #address-cells = <1>;9 #size-cells = <1>;11 interrupt-parent = <&aic>;14 #address-cells = <1>;15 #size-cells = <0>;21 clock-frequency = <50000000>;22 d-cache-size = <8192>;[all …]
... ] = 0x%02lx) L1: D-cache 32 KiB enabled I-cache 32 KiB ...
2 * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.4 * Copyright (C) 2002-2011 Aleph One Ltd.53 chunk = (u32) (addr >> dev->chunk_shift); in yaffs_addr_to_chunk()55 if (dev->chunk_div == 1) { in yaffs_addr_to_chunk()57 offset = (u32) (addr & dev->chunk_mask); in yaffs_addr_to_chunk()59 /* Non power-of-2 case */ in yaffs_addr_to_chunk()63 chunk /= dev->chunk_div; in yaffs_addr_to_chunk()65 chunk_base = ((loff_t) chunk) * dev->data_bytes_per_chunk; in yaffs_addr_to_chunk()66 offset = (u32) (addr - chunk_base); in yaffs_addr_to_chunk()128 memset(dev->temp_buffer, 0, sizeof(dev->temp_buffer)); in yaffs_init_tmp_buffers()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright © 2009 - Maxim Levitsky16 #include <linux/mtd/nand-ecc-sw-hamming.h>27 "Timeout (in ms) for cache flush (1000 ms default");31 MODULE_PARM_DESC(debug, "Debug level (0-2)");34 /* ------------------- sysfs attributes ---------------------------------- */47 strncpy(buf, sm_attr->data, sm_attr->len); in sm_attr_show()48 return sm_attr->len; in sm_attr_show()61 vendor = kstrndup(ftl->cis_buffer + SM_CIS_VENDOR_OFFSET, in sm_create_sysfs_attributes()62 SM_SMALL_PAGE - SM_CIS_VENDOR_OFFSET, GFP_KERNEL); in sm_create_sysfs_attributes()[all …]
9 .. list-table:: Supported Guest Architectures for Emulation11 :header-rows: 113 * - Architecture (qemu name)14 - System15 - User16 - Notes17 * - Alpha18 - Yes19 - Yes20 - Legacy 64 bit RISC ISA developed by DEC[all …]
1 // SPDX-License-Identifier: MIT10 * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears11 * 512 bytes of Render Cache.20 * DW 1.0 - Block Offset to write Render Cache21 * DW 1.1 [15:0] - Clear Word22 * DW 1.2 - Delay iterations23 * DW 1.3 - Enable Instrumentation (only for debug)24 * DW 1.4 - Rsvd (intended for context ID)25 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount26 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)[all …]