/openbmc/linux/drivers/iommu/arm/arm-smmu/ |
H A D | qcom_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c 13 #include <linux/dma-mapping.h> 17 #include <linux/io-64-nonatomic-hi-lo.h> 18 #include <linux/io-pgtable.h> 33 #include "arm-smmu.h" 54 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */ 62 u8 asid; /* asid and ctx bank # are 1:1 */ member 86 if (!fwspec || fwspec->ops != &qcom_iommu_ops) in to_iommu() 92 static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid) in to_ctx() argument [all …]
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/openbmc/linux/drivers/accel/habanalabs/common/ |
H A D | context.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2016-2021 HabanaLabs, Ltd. 15 struct hl_encaps_signals_mgr *mgr = &handle->ctx->sig_mgr; in encaps_handle_do_release() 18 hw_sob_put(handle->hw_sob); in encaps_handle_do_release() 20 spin_lock(&mgr->lock); in encaps_handle_do_release() 21 idr_remove(&mgr->handles, handle->id); in encaps_handle_do_release() 22 spin_unlock(&mgr->lock); in encaps_handle_do_release() 25 hl_ctx_put(handle->ctx); in encaps_handle_do_release() 56 spin_lock_init(&mgr->lock); in hl_encaps_sig_mgr_init() 57 idr_init(&mgr->handles); in hl_encaps_sig_mgr_init() [all …]
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H A D | memory.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2016-2022 HabanaLabs, Ltd. 15 #include <linux/pci-p2pdma.h> 21 /* use small pages for supporting non-pow2 (32M/40M/48M) DRAM phys page sizes */ 31 struct asic_fixed_properties *prop = &hdev->asic_prop; in set_alloc_page_size() 38 if (prop->supports_user_set_page_size && args->alloc.page_size) { in set_alloc_page_size() 39 psize = args->alloc.page_size; in set_alloc_page_size() 42 dev_err(hdev->dev, "user page size (%#llx) is not power of 2\n", psize); in set_alloc_page_size() 43 return -EINVAL; in set_alloc_page_size() 46 psize = prop->device_mem_alloc_default_page_size; in set_alloc_page_size() [all …]
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H A D | debugfs.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2016-2021 HabanaLabs, Ltd. 30 return -EBUSY; in hl_debugfs_i2c_read() 33 dev_err(hdev->dev, "I2C transaction length %u, exceeds maximum of %u\n", in hl_debugfs_i2c_read() 35 return -EINVAL; in hl_debugfs_i2c_read() 47 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), in hl_debugfs_i2c_read() 50 dev_err(hdev->dev, "Failed to read from I2C, error %d\n", rc); in hl_debugfs_i2c_read() 62 return -EBUSY; in hl_debugfs_i2c_write() 65 dev_err(hdev->dev, "I2C transaction length %u, exceeds maximum of %u\n", in hl_debugfs_i2c_write() 67 return -EINVAL; in hl_debugfs_i2c_write() [all …]
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H A D | command_submission.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2016-2021 HabanaLabs, Ltd. 23 * enum hl_cs_wait_status - cs wait status 35 static int _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq, 48 * push outcome - store a recent CS outcome in the store in hl_push_cs_outcome() 49 * pop outcome - retrieve a SPECIFIC (by seq) CS outcome from the store in hl_push_cs_outcome() 51 * It has a pre-allocated amount of nodes, each node stores in hl_push_cs_outcome() 66 spin_lock_irqsave(&outcome_store->db_lock, flags); in hl_push_cs_outcome() 68 if (list_empty(&outcome_store->free_list)) { in hl_push_cs_outcome() 69 node = list_last_entry(&outcome_store->used_list, in hl_push_cs_outcome() [all …]
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H A D | habanalabs.h | 1 /* SPDX-License-Identifier: GPL-2.0 3 * Copyright 2016-2022 HabanaLabs, Ltd. 19 #include <linux/dma-direction.h> 28 #include <linux/io-64-nonatomic-lo-hi.h> 30 #include <linux/dma-buf.h> 42 * bits[63:59] - Encode mmap type 43 * bits[45:0] - mmap offset value 48 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT) 107 * enum hl_mmu_page_table_location - mmu page table location 108 * @MMU_DR_PGT: page-table is located on device DRAM. [all …]
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H A D | command_buffer.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2016-2019 HabanaLabs, Ltd. 17 static int cb_map_mem(struct hl_ctx *ctx, struct hl_cb *cb) in cb_map_mem() argument 19 struct hl_device *hdev = ctx->hdev; in cb_map_mem() 20 struct asic_fixed_properties *prop = &hdev->asic_prop; in cb_map_mem() 21 u32 page_size = prop->pmmu.page_size; in cb_map_mem() 24 if (!hdev->supports_cb_mapping) { in cb_map_mem() 25 dev_err_ratelimited(hdev->dev, in cb_map_mem() 27 return -EINVAL; in cb_map_mem() 30 if (cb->is_mmu_mapped) in cb_map_mem() [all …]
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/openbmc/linux/arch/mips/mm/ |
H A D | context.c | 1 // SPDX-License-Identifier: GPL-2.0 24 u64 asid; in get_new_mmu_context() local 34 asid = asid_cache(cpu); in get_new_mmu_context() 36 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) { in get_new_mmu_context() 39 local_flush_tlb_all(); /* start new asid cycle */ in get_new_mmu_context() 42 set_cpu_context(cpu, mm, asid); in get_new_mmu_context() 43 asid_cache(cpu) = asid; in get_new_mmu_context() 58 /* Check if our ASID is of an older version and thus invalid */ in check_mmu_context() 94 * context-switch in flush_context() 146 * We had a valid MMID in a previous life, so try to re-use in get_new_mmid() [all …]
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/openbmc/linux/drivers/vhost/ |
H A D | vdpa.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2018-2020 Intel Corporation. 70 u64 last, u32 asid); 76 return as->id; in iotlb_to_asid() 79 static struct vhost_vdpa_as *asid_to_as(struct vhost_vdpa *v, u32 asid) in asid_to_as() argument 81 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in asid_to_as() 85 if (as->id == asid) in asid_to_as() 91 static struct vhost_iotlb *asid_to_iotlb(struct vhost_vdpa *v, u32 asid) in asid_to_iotlb() argument 93 struct vhost_vdpa_as *as = asid_to_as(v, asid); in asid_to_iotlb() 98 return &as->iotlb; in asid_to_iotlb() [all …]
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H A D | vhost.c | 1 // SPDX-License-Identifier: GPL-2.0-only 49 #define vhost_used_event(vq) ((__virtio16 __user *)&vq->avail->ring[vq->num]) 50 #define vhost_avail_event(vq) ((__virtio16 __user *)&vq->used->ring[vq->num]) 55 vq->user_be = !virtio_legacy_is_little_endian(); in vhost_disable_cross_endian() 60 vq->user_be = true; in vhost_enable_cross_endian_big() 65 vq->user_be = false; in vhost_enable_cross_endian_little() 72 if (vq->private_data) in vhost_set_vring_endian() 73 return -EBUSY; in vhost_set_vring_endian() 76 return -EFAULT; in vhost_set_vring_endian() 80 return -EINVAL; in vhost_set_vring_endian() [all …]
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H A D | vhost.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 76 struct eventfd_ctx *ctx; member 147 /* Ring endianness requested by userspace for cross-endian support. */ 179 int (*msg_handler)(struct vhost_dev *dev, u32 asid, 187 int (*msg_handler)(struct vhost_dev *dev, u32 asid, 253 if ((vq)->error_ctx) \ 254 eventfd_signal((vq)->error_ctx, 1);\ 267 * vhost_vq_set_backend - Set backend. 272 * Context: Need to call with vq->mutex acquired. 277 vq->private_data = private_data; in vhost_vq_set_backend() [all …]
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/openbmc/linux/arch/mips/include/asm/ |
H A D | mmu_context.h | 26 #include <asm-generic/mm_hooks.h> 80 * allow the kernel to create wired entries with the MMID of current->active_mm 92 * as a software asid extension. 98 return ~(u64)(asid_mask | (asid_mask - 1)); in asid_version_mask() 109 return atomic64_read(&mm->context.mmid); in cpu_context() 111 return mm->context.asid[cpu]; in cpu_context() 115 struct mm_struct *mm, u64 ctx) in set_cpu_context() argument 118 atomic64_set(&mm->context.mmid, ctx); in set_cpu_context() 120 mm->context.asid[cpu] = ctx; in set_cpu_context() 148 mm->context.bd_emupage_allocmap = NULL; in init_new_context() [all …]
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/openbmc/linux/drivers/accel/habanalabs/common/mmu/ |
H A D | mmu.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2016-2022 HabanaLabs, Ltd. 15 * hl_mmu_get_funcs() - get MMU functions structure 25 return &hdev->mmu_func[pgt_residency]; in hl_mmu_get_funcs() 30 struct asic_fixed_properties *prop = &hdev->asic_prop; in hl_is_dram_va() 32 return hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size, in hl_is_dram_va() 33 prop->dmmu.start_addr, in hl_is_dram_va() 34 prop->dmmu.end_addr); in hl_is_dram_va() 38 * hl_mmu_init() - initialize the MMU module. 41 * Return: 0 for success, non-zero for failure. [all …]
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H A D | mmu_v1.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2016-2019 HabanaLabs, Ltd. 15 static inline u64 get_phys_addr(struct hl_ctx *ctx, u64 shadow_addr); 17 static struct pgt_info *get_pgt_info(struct hl_ctx *ctx, u64 hop_addr) in get_pgt_info() argument 21 hash_for_each_possible(ctx->mmu_shadow_hash, pgt_info, node, in get_pgt_info() 23 if (hop_addr == pgt_info->shadow_addr) in get_pgt_info() 29 static void _free_hop(struct hl_ctx *ctx, struct pgt_info *pgt_info) in _free_hop() argument 31 struct hl_device *hdev = ctx->hdev; in _free_hop() 33 gen_pool_free(hdev->mmu_priv.dr.mmu_pgt_pool, pgt_info->phys_addr, in _free_hop() 34 hdev->asic_prop.mmu_hop_table_size); in _free_hop() [all …]
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H A D | mmu_v2_hr.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2020-2022 HabanaLabs, Ltd. 13 static struct pgt_info *hl_mmu_v2_hr_get_pgt_info(struct hl_ctx *ctx, u64 phys_hop_addr) in hl_mmu_v2_hr_get_pgt_info() argument 17 hash_for_each_possible(ctx->hr_mmu_phys_hash, pgt_info, node, in hl_mmu_v2_hr_get_pgt_info() 19 if (phys_hop_addr == pgt_info->phys_addr) in hl_mmu_v2_hr_get_pgt_info() 25 static void hl_mmu_v2_hr_add_pgt_info(struct hl_ctx *ctx, struct pgt_info *pgt_info, in hl_mmu_v2_hr_add_pgt_info() argument 28 hash_add(ctx->hr_mmu_phys_hash, &pgt_info->node, phys_addr); in hl_mmu_v2_hr_add_pgt_info() 31 static struct pgt_info *hl_mmu_v2_hr_get_hop0_pgt_info(struct hl_ctx *ctx) in hl_mmu_v2_hr_get_hop0_pgt_info() argument 33 return &ctx->hdev->mmu_priv.hr.mmu_asid_hop0[ctx->asid]; in hl_mmu_v2_hr_get_hop0_pgt_info() 37 * hl_mmu_v2_hr_init() - initialize the MMU module. [all …]
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/openbmc/linux/arch/m68k/include/asm/ |
H A D | mmu_context.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 5 #include <asm-generic/mm_hooks.h> 30 mm_context_t ctx; in get_mmu_context() local 32 if (mm->context != NO_CONTEXT) in get_mmu_context() 38 ctx = next_mmu_context; in get_mmu_context() 39 while (test_and_set_bit(ctx, context_map)) { in get_mmu_context() 40 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); in get_mmu_context() 41 if (ctx > LAST_CONTEXT) in get_mmu_context() 42 ctx = 0; in get_mmu_context() 44 next_mmu_context = (ctx + 1) & LAST_CONTEXT; in get_mmu_context() [all …]
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/openbmc/linux/drivers/accel/habanalabs/gaudi/ |
H A D | gaudi.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2016-2022 HabanaLabs, Ltd. 27 * - Range registers 28 * - MMU 31 * - Range registers (protect the first 512MB) 34 * - Range registers 35 * - Protection bits 40 * - DMA is not secured. 41 * - PQ and CQ are secured. 42 * - CP is secured: The driver needs to parse CB but WREG should be allowed [all …]
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/openbmc/linux/Documentation/devicetree/bindings/iommu/ |
H A D | qcom,iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Konrad Dybcio <konrad.dybcio@linaro.org> 13 Qualcomm "B" family devices which are not compatible with arm-smmu have 16 to non-secure vs secure interrupt line. 21 - items: 22 - enum: 23 - qcom,msm8916-iommu 24 - qcom,msm8953-iommu [all …]
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/openbmc/linux/drivers/accel/habanalabs/gaudi2/ |
H A D | gaudi2.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright 2020-2022 HabanaLabs, Ltd. 45 * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs 127 #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0) 128 #define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0) 132 #define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \ 135 #define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0) 165 /* HW scrambles only bits 0-25 */ 2015 * and read global errors. Most HW blocks are addressable and those who aren't (N/A)- 2038 {HBM_MC_SPI_THR_ENG_MASK, "temperature-based throttling engaged"}, [all …]
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/openbmc/linux/drivers/misc/sgi-gru/ |
H A D | grumain.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 56 /*--------- ASID Management ------------------------------------------- 62 * asid in use ("x"s below). Set "limit" to this value. 70 * Each time MAX_ASID is reached, increment the asid generation. Since 71 * the search for in-use asids only checks contexts with GRUs currently 73 * a context, the asid generation of the GTS asid is rechecked. If it 74 * doesn't match the current generation, a new asid will be assigned. 76 * 0---------------x------------x---------------------x----| 77 * ^-next ^-limit ^-MAX_ASID 79 * All asid manipulation & context loading/unloading is protected by the [all …]
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H A D | grutables.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 28 * +-----------------+ 37 * +-----------------+ 39 * +-----------------+ _______ +-------------+ 45 * |/////////////////| / |-------------| 47 * +-----------------+ | | 49 * +-----------------+ | | 51 * +-----------------+ \____________ +-------------+ 53 * +-----------------+ 55 * +-----------------+ [all …]
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H A D | gruprocfs.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 122 seq_puts(s, "#id count aver-clks max-clks\n"); in mcs_statistics_show() 127 seq_printf(s, "%-20s%12ld%12ld%12ld\n", id[op], count, in mcs_statistics_show() 168 seq_puts(file, "# gid bid ctx# asid pid cbrs dsbytes mode\n"); in cch_seq_show() 171 ts = gru->gs_gts[i]; in cch_seq_show() 175 gru->gs_gid, gru->gs_blade_id, i, in cch_seq_show() 176 is_kernel_context(ts) ? 0 : ts->ts_gms->ms_asids[gid].mt_asid, in cch_seq_show() 177 is_kernel_context(ts) ? 0 : ts->ts_tgid_owner, in cch_seq_show() 178 ts->ts_cbr_au_count * GRU_CBR_AU_SIZE, in cch_seq_show() 179 ts->ts_cbr_au_count * GRU_DSR_AU_BYTES, in cch_seq_show() [all …]
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/openbmc/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_privileged.c.inc | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 8 #include "cpu-csr.h" 13 static bool trans_##name(DisasContext *ctx, arg_##name * a) \ 94 CSR_OFF_FUNCS(ASID, CSRFL_EXITTB, NULL, gen_helper_csrwr_asid), 154 static bool check_plv(DisasContext *ctx) 156 if (ctx->plv == MMU_PLV_USER) { 157 generate_exception(ctx, EXCCODE_IPE); 171 if (csr->offset == 0) { 177 static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write) 179 if ((csr->flags & CSRFL_READONLY) && write) { [all …]
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/openbmc/linux/drivers/accel/habanalabs/goya/ |
H A D | goyaP.h | 1 /* SPDX-License-Identifier: GPL-2.0 3 * Copyright 2016-2022 HabanaLabs, Ltd. 126 #define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */ 127 #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \ 132 #define VA_DDR_SPACE_SIZE (VA_DDR_SPACE_END - \ 195 int goya_context_switch(struct hl_device *hdev, u32 asid); 223 int goya_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data); 224 void goya_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
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/openbmc/linux/arch/x86/include/asm/ |
H A D | tlbflush.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 15 #include <asm/processor-flags.h> 22 #define TLB_FLUSH_ALL -1UL 75 * are on. This means that it may not match current->active_mm, 80 * LOADED_MM_SWITCHING during the brief interrupts-off window 100 * This tells us to go invalidate all the non-loaded ctxs[] 103 * The current ctx was kept up-to-date as it ran and does not 133 * There is one per ASID that we use, and the ASID (what the 138 * contain entries that are out-of-date as when that mm reached 146 * various bits of init code. This is fine -- code that [all …]
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