/openbmc/linux/Documentation/devicetree/bindings/mmc/ |
H A D | snps,dwcmshc-sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com> 14 - $ref: mmc-controller.yaml# 19 - rockchip,rk3568-dwcmshc 20 - rockchip,rk3588-dwcmshc 21 - snps,dwcmshc-sdhci [all …]
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/openbmc/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3399.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <clk-uclass.h> 10 #include <dt-structs.h> 20 #include <dt-bindings/clock/rk3399-cru.h> 41 ((input_rate) / (output_rate) - 1); 234 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 238 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 306 * FOUTVCO = Fractional PLL non-divided output frequency 317 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll() 318 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll() [all …]
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H A D | clk_rk3288.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <clk-uclass.h> 11 #include <dt-structs.h> 20 #include <dt-bindings/clock/rk3288-cru.h> 21 #include <dm/device-internal.h> 23 #include <dm/uclass-internal.h> 72 /* CLKSEL1: pd bus clk pll sel: codec or general */ 77 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ 81 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 85 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ [all …]
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H A D | clk_rk3128.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <clk-uclass.h> 17 #include <dt-bindings/clock/rk3128-cru.h> 38 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument 42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() 45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll() 46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll() 49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll() 50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll() 55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll() [all …]
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H A D | clk_rk3036.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <clk-uclass.h> 16 #include <dt-bindings/clock/rk3036-cru.h> 27 ((input_rate) / (output_rate) - 1); 44 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument 48 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() 51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll() 52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll() 56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll() 57 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll() [all …]
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H A D | clk_rk322x.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <clk-uclass.h> 16 #include <dt-bindings/clock/rk3228-cru.h> 41 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument 45 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() 48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll() 49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll() 52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll() 53 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll() 58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll() [all …]
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/openbmc/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3066a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/pinctrl/rockchip.h> 9 #include <dt-bindings/clock/rk3066a-cru.h> 10 #include <dt-bindings/power/rk3066-power.h> 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; [all …]
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H A D | rk3188.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/pinctrl/rockchip.h> 9 #include <dt-bindings/clock/rk3188-cru.h> 10 #include <dt-bindings/power/rk3188-power.h> 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; [all …]
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H A D | rk3036.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 #include <dt-bindings/gpio/gpio.h> 4 #include <dt-bindings/interrupt-controller/irq.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 7 #include <dt-bindings/clock/rk3036-cru.h> 8 #include <dt-bindings/soc/rockchip,boot-mode.h> 9 #include <dt-bindings/power/rk3036-power.h> 12 #address-cells = <1>; 13 #size-cells = <1>; [all …]
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/openbmc/linux/drivers/media/platform/renesas/rzg2l-cru/ |
H A D | rzg2l-video.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Driver for Renesas RZ/G2L CRU 7 * Based on Renesas R-Car VIN 9 * Copyright (C) 2011-2013 Renesas Solutions Corp. 18 #include <media/v4l2-ioctl.h> 19 #include <media/videobuf2-dma-contig.h> 21 #include "rzg2l-cru.h" 23 /* HW CRU Registers Definition */ 25 /* CRU Control Register */ 29 /* CRU Interrupt Enable Register */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Lin <shawn.lin@rock-chips.com> 13 - $ref: /schemas/pci/pci-bus.yaml# 14 - $ref: rockchip,rk3399-pcie-common.yaml# 18 const: rockchip,rk3399-pcie 22 reg-names: 24 - const: axi-base [all …]
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H A D | rockchip,rk3399-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Lin <shawn.lin@rock-chips.com> 13 - $ref: /schemas/pci/pci-ep.yaml# 14 - $ref: rockchip,rk3399-pcie-common.yaml# 18 const: rockchip,rk3399-pcie-ep 22 reg-names: 24 - const: apb-base [all …]
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H A D | rockchip-dw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Lin <shawn.lin@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com> 12 - Heiko Stuebner <heiko@sntech.de> 17 snps,dw-pcie.yaml. 20 - $ref: /schemas/pci/snps,dw-pcie.yaml# 25 - const: rockchip,rk3568-pcie [all …]
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/openbmc/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3588.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "rk3588-pinctrl.dtsi" 11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 21 compatible = "rockchip,rk3588-i2s-tdm"; 24 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 25 clock-names = "mclk_tx", "mclk_rx", "hclk"; 26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 27 assigned-clock-parents = <&cru PLL_AUPLL>; 29 dma-names = "tx"; [all …]
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H A D | rk3568.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 14 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, 15 <&cru CLK_SATA0_RXOOB>; 16 clock-names = "sata", "pmalive", "rxoob"; 19 phy-names = "sata-phy"; 20 ports-implemented = <0x1>; 21 power-domains = <&power RK3568_PD_PIPE>; 26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 31 compatible = "rockchip,rk3568-qos", "syscon"; [all …]
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H A D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rk3399-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3399-power.h> 12 #include <dt-bindings/thermal/thermal.h> 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | rockchip,i2s-tdm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com> 18 - $ref: dai-common.yaml# 23 - rockchip,px30-i2s-tdm 24 - rockchip,rk1808-i2s-tdm 25 - rockchip,rk3308-i2s-tdm 26 - rockchip,rk3568-i2s-tdm [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3188.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR X11 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/pinctrl/rockchip.h> 9 #include <dt-bindings/clock/rk3188-cru.h> 16 #address-cells = <1>; 17 #size-cells = <0>; 18 enable-method = "rockchip,rk3066-smp"; 22 compatible = "arm,cortex-a9"; 23 next-level-cache = <&L2>; 25 operating-points = < [all …]
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H A D | rk322x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/clock/rk3228-cru.h> 11 #include <dt-bindings/thermal/thermal.h> 14 #address-cells = <1>; 15 #size-cells = <1>; 17 interrupt-parent = <&gic>; [all …]
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H A D | rk3036.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 #include <dt-bindings/gpio/gpio.h> 4 #include <dt-bindings/interrupt-controller/irq.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 7 #include <dt-bindings/clock/rk3036-cru.h> 13 interrupt-parent = <&gic>; 32 arm-pmu { 33 compatible = "arm,cortex-a7-pmu"; 36 interrupt-affinity = <&cpu0>, <&cpu1>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | rockchip-isp1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 --- 4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Helen Koike <helen.koike@collabora.com> 19 - rockchip,px30-cif-isp 20 - rockchip,rk3399-cif-isp 29 interrupt-names: 31 - const: isp 32 - const: mi [all …]
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H A D | renesas,rzg2l-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 14 The CRU image processing module is a data conversion module equipped with pixel 15 color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and 16 parallel (including ITU-R BT.656) input are provided as the image sensor interface. 21 - enum: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | rockchip,rk3399-dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 14 const: rockchip,rk3399-dwc3 16 '#address-cells': 19 '#size-cells': 26 - description: 28 - description: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/ |
H A D | rockchip-vop2.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 15 - Sandy Huang <hjc@rock-chips.com> 16 - Heiko Stuebner <heiko@sntech.de> 21 - rockchip,rk3566-vop 22 - rockchip,rk3568-vop 26 - description: 29 - description: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/spi/ |
H A D | rockchip-sfc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 11 - Chris Morgan <macromorgan@hotmail.com> 14 - $ref: spi-controller.yaml# 32 - description: Bus Clock 33 - description: Module Clock 35 clock-names: [all …]
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