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Searched +full:cros +full:- +full:ec +full:- +full:spi +full:- +full:pre +full:- +full:delay (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Guenter Roeck <groeck@chromium.org>
14 Google's ChromeOS EC is a microcontroller which talks to the AP and
16 The EC can be connected through various interfaces (I2C, SPI, and others)
22 - description:
23 For implementations of the EC connected through I2C.
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/openbmc/u-boot/arch/arm/dts/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288-veyron.dtsi"
19 gpio_keys: gpio-keys {
20 pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
25 linux,input-type = <5>; /* EV_SW */
26 debounce-interval = <1>;
27 gpio-key,wakeup;
31 gpio-charger {
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H A Dtegra124-nyan-big-u-boot.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include "tegra-u-boot.dtsi"
11 u-boot,dm-pre-reloc;
13 u-boot,dm-pre-reloc;
17 spi@7000d400 {
18 spi-deactivate-delay = <500>;
19 spi-max-frequency = <3000000>;
21 cros_ec: cros-ec@0 {
22 ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
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H A Dexynos5250-snow.dts12 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/input/input.h>
32 spi0 = "/spi@12d20000";
33 spi1 = "/spi@12d30000";
34 spi2 = "/spi@12d40000";
35 spi3 = "/spi@131a0000";
36 spi4 = "/spi@131b0000";
51 stdout-path = "serial3:115200n8";
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H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/input/input.h>
29 spi0 = "/spi@12d20000";
30 spi1 = "/spi@12d30000";
31 spi2 = "/spi@12d40000";
32 spi3 = "/spi@131a0000";
33 spi4 = "/spi@131b0000";
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/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/rockchip,rk808.h>
10 #include <dt-bindings/input/input.h>
11 #include "rk3288-veyron.dtsi"
12 #include "rk3288-veyron-analog-audio.dtsi"
13 #include "rk3288-veyron-edp.dtsi"
14 #include "rk3288-veyron-sdmmc.dtsi"
22 gpio-charger {
23 compatible = "gpio-charger";
24 charger-type = "mains";
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/openbmc/linux/drivers/platform/chrome/
H A Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
2 // SPI interface for ChromeOS Embedded Controller
6 #include <linux/delay.h>
14 #include <linux/spi/spi.h>
23 * Number of EC preamble bytes we read at a time. Since it takes
24 * about 400-500us for the EC to respond there is not a lot of
25 * point in tuning this. If the EC could respond faster then
28 * SPI transfer size is 256 bytes, so at 5MHz we need a response
34 * Allow for a long time for the EC to respond. We support i2c
50 * for this, clocking in at 2-3ms.
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/openbmc/u-boot/arch/x86/dts/
H A Dchromebook_link.dts1 /dts-v1/;
3 #include <dt-bindings/gpio/x86-gpio.h>
4 #include <dt-bindings/sound/azalia.h>
16 compatible = "google,link", "intel,celeron-ivybridge";
19 spi0 = &spi;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "intel,core-gen3";
36 intel,apic-id = <0>;
41 compatible = "intel,core-gen3";
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H A Dchromebook_samus.dts1 /dts-v1/;
3 #include <dt-bindings/gpio/x86-gpio.h>
17 spi0 = &spi;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "intel,core-i3-gen5";
34 intel,apic-id = <0>;
35 intel,slow-ramp = <3>;
40 compatible = "intel,core-i3-gen5";
42 intel,apic-id = <1>;
[all …]
/openbmc/u-boot/include/
H A Dec_commands.h2 * Use of this source code is governed by a BSD-style license that can be
6 /* Host communication command constants for Chrome EC */
18 * - CMD is the command code. (defined by EC_CMD_ constants)
19 * - ERR is the error code. (defined by EC_RES_ constants)
20 * - Px is the optional payload.
23 * - S is the checksum which is the sum of all payload bytes.
59 /* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
65 /* EC command register bit functions */
67 #define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */
68 #define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */
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/openbmc/linux/include/linux/platform_data/
H A Dcros_ec_commands.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Host communication command constants for ChromeOS EC
7 * NOTE: This file is auto-generated from ChromeOS EC Open Source code from
8 * https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/ec_commands.h
11 /* Host communication command constants for Chrome EC */
52 * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
56 * MEC series EC; an attempt to address a larger region may fail.
63 /* EC command register bit functions */
65 #define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */
66 #define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */
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/openbmc/linux/
H A DMAINTAINERS5 ----------
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H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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/openbmc/
Dopengrok1.0.log1 2025-01-07 03:00:34.968-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-01-07 03:00:35.081-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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Dopengrok2.0.log1 2025-01-06 03:00:36.640-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-01-06 03:00:36.753-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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