Home
last modified time | relevance | path

Searched +full:cros +full:- +full:ec +full:- +full:i2c (Results 1 – 25 of 27) sorted by relevance

12

/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dcros-ec.txt8 - compatible = "google,cros-ec"
11 - spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
13 - i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
15 - ec-interrupt : Selects the EC interrupt, defined as a GPIO according
17 - optimise-flash-write : Boolean property - if present then flash blocks
18 containing all 0xff will not be written, since we assume that the EC
22 to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
30 cros-ec@0 {
32 compatible = "google,cros-ec";
33 spi-max-frequency = <5000000>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/i2c/
H A Di2c.txt1 U-Boot I2C
2 ----------
4 U-Boot's I2C model has the concept of an offset within a chip (I2C target
9 Apart from the controller-specific I2C bindings, U-Boot supports a special
13 - u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the
15 - gpios = <sda ...>, <scl ...>;
16 pinctrl-names = "default", "gpio";
17 pinctrl-0 = <&i2c_xfer>;
18 pinctrl-1 = <&i2c_gpio>;
19 Pin description for I2C bus software deblocking.
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288-veyron.dtsi"
19 gpio_keys: gpio-keys {
20 pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
25 linux,input-type = <5>; /* EV_SW */
26 debounce-interval = <1>;
27 gpio-key,wakeup;
31 gpio-charger {
[all …]
H A Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
14 cpu-model = "Exynos5800";
16 compatible = "google,pit-rev#", "google,pit",
20 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
21 hwid = "PIT TEST A-A 7848";
22 lazy-init = <1>;
28 pmic = "/i2c@12CA0000";
33 compatible = "pwm-backlight";
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
[all …]
H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
11 #include <dt-bindings/clock/maxim,max77802.h>
12 #include <dt-bindings/regulator/maxim,max77802.h>
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
29 pmic = "/i2c@12CA0000";
[all …]
H A Dcros-ec-sbs.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Smart battery dts fragment for devices that use cros-ec-sbs
9 battery: sbs-battery@b {
10 compatible = "sbs,sbs-battery";
12 sbs,i2c-retry-count = <2>;
13 sbs,poll-retry-count = <1>;
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
15 /* EC turns on w/ pp900_ap_en; always on for AP */
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
[all …]
H A Dexynos5250-snow.dts12 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/input/input.h>
23 i2c0 = "/i2c@12C60000";
24 i2c1 = "/i2c@12C70000";
25 i2c2 = "/i2c@12C80000";
26 i2c3 = "/i2c@12C90000";
27 i2c4 = "/i2c@12CA0000";
29 i2c5 = "/i2c@12CB0000";
[all …]
H A Dtegra124-nyan.dtsi1 #include <dt-bindings/input/input.h>
6 rtc0 = "/i2c@7000d000/pmic@40";
19 vdd-supply = <&vdd_3v3_hdmi>;
20 pll-supply = <&vdd_hdmi_pll>;
21 hdmi-supply = <&vdd_5v0_hdmi>;
23 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
24 nvidia,hpd-gpio =
36 vdd-supply = <&vdd_3v3_panel>;
50 i2c@7000c000 {
52 clock-frequency = <100000>;
[all …]
H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/input/input.h>
20 i2c0 = "/i2c@12C60000";
21 i2c1 = "/i2c@12C70000";
22 i2c2 = "/i2c@12C80000";
23 i2c3 = "/i2c@12C90000";
24 i2c4 = "/i2c@12CA0000";
[all …]
H A Drk3288-veyron-jerry.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
14 compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
15 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
16 "google,veyron-jerry-rev3", "google,veyron-jerry",
20 stdout-path = &uart2;
23 panel_regulator: panel-regulator {
24 compatible = "regulator-fixed";
[all …]
/openbmc/u-boot/include/
H A Dcros_ec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
20 struct gpio_desc ec_int; /* GPIO used as EC interrupt line */
25 * These two buffers will always be dword-aligned and include enough
26 * space for up to 7 word-alignment bytes also, so we can ensure that
27 * the body of the message is always dword-aligned (64-bit).
40 * Hard-code the number of columns we happen to know we have right now. It
51 /* Holds information about the Chrome EC */
53 struct fmap_entry flash; /* Address and size of EC flash */
55 * Byte value of erased flash, or -1 if not known. It is normally
63 * Read the ID of the CROS-EC device
[all …]
H A Dec_commands.h2 * Use of this source code is governed by a BSD-style license that can be
6 /* Host communication command constants for Chrome EC */
18 * - CMD is the command code. (defined by EC_CMD_ constants)
19 * - ERR is the error code. (defined by EC_RES_ constants)
20 * - Px is the optional payload.
23 * - S is the checksum which is the sum of all payload bytes.
27 * On I2C, all bytes are sent serially in the same message.
59 /* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
65 /* EC command register bit functions */
67 #define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */
[all …]
/openbmc/u-boot/arch/sandbox/dts/
H A Dsandbox64.dts1 /dts-v1/;
6 #address-cells = <2>;
7 #size-cells = <2>;
17 stdout-path = "/serial";
20 cros_ec: cros-ec {
22 compatible = "google,cros-ec-sandbox";
25 * This describes the flash memory within the EC. Note
29 image-pos = <0x08000000>;
31 erase-value = <0>;
35 image-pos = <0>;
[all …]
H A Dsandbox.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
18 stdout-path = "/serial";
21 audio: audio-codec {
22 compatible = "sandbox,audio-codec";
23 #sound-dai-cells = <1>;
26 cros_ec: cros-ec {
28 u-boot,dm-pre-reloc;
29 compatible = "google,cros-ec-sandbox";
[all …]
H A Dtest.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
16 i2c0 = "/i2c@0";
27 testfdt6 = "/e-test";
28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dcros_ec_tunnel.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <i2c.h>
29 return cros_ec_i2c_tunnel(dev->parent, i2c_bus->remote_bus, msg, nmsgs); in cros_ec_i2c_xfer()
35 const void *blob = gd->fdt_blob; in cros_ec_i2c_ofdata_to_platdata()
38 i2c_bus->remote_bus = fdtdec_get_uint(blob, node, "google,remote-bus", in cros_ec_i2c_ofdata_to_platdata()
50 { .compatible = "google,cros-ec-i2c-tunnel" },
H A Dcros_ec_ldo.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <i2c.h>
29 if (!nmsgs || !msg->len || (msg->flags & I2C_M_RD)) { in cros_ec_ldo_xfer()
34 fet_id = msg->buf[0] - REG_FET_BASE; in cros_ec_ldo_xfer()
43 ret = cros_ec_get_ldo(dev->parent, fet_id, &state); in cros_ec_ldo_xfer()
48 bool on = msg->buf[1] & FET_CTRL_ENFET; in cros_ec_ldo_xfer()
50 ret = cros_ec_set_ldo(dev->parent, fet_id, on); in cros_ec_ldo_xfer()
57 return -ENOSYS; in cros_ec_ldo_xfer()
66 { .compatible = "google,cros-ec-ldo-tunnel" },
/openbmc/u-boot/drivers/misc/
H A Dcros_ec.c1 // SPDX-License-Identifier: GPL-2.0+
9 * This is the interface to the Chrome OS EC. It provides keyboard functions,
11 * provided to enable the EC software to be updated, talk to the EC's I2C bus
12 * and store a small amount of data in a memory which persists while the EC
21 #include <i2c.h>
28 #include <asm-generic/gpio.h>
29 #include <dm/device-internal.h>
31 #include <dm/uclass-internal.h>
49 * Map UHEPI masks to non UHEPI commands in order to support old EC FW
100 if (cmd != -1) in cros_ec_dump_data()
[all …]
H A Dcros_ec_i2c.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Chromium OS cros_ec driver - I2C interface
17 #include <i2c.h>
29 * byte 1-8 struct ec_host_request
30 * byte 10- response data
42 * byte 2-9 struct ec_host_response
43 * byte 10- response data
56 (struct ec_host_request_i2c *)dev->dout; in cros_ec_i2c_packet()
58 (struct ec_host_response_i2c *)dev->din; in cros_ec_i2c_packet()
62 i2c_msg[0].addr = chip->chip_addr; in cros_ec_i2c_packet()
[all …]
/openbmc/u-boot/include/configs/
H A Dtegra-common-post.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2012
36 #define STDIN_KBD_KBC ",tegra-kbc"
61 #define STDOUT_CROS_EC ",cros-ec-keyb"
108 /* remove I2C support */
/openbmc/u-boot/board/samsung/common/
H A Dboard.c1 // SPDX-License-Identifier: GPL-2.0+
25 #include <i2c.h>
27 #include <dwc3-uboot.h>
80 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); in board_init()
82 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { in board_init()
84 return -1; in board_init()
92 gd->ram_size -= size; in board_init()
93 gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; in board_init()
105 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); in dram_init()
119 gd->bd->bi_dram[i].start = addr; in dram_init_banksize()
[all …]
/openbmc/u-boot/arch/x86/dts/
H A Dchromebook_samus.dts1 /dts-v1/;
3 #include <dt-bindings/gpio/x86-gpio.h>
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "intel,core-i3-gen5";
34 intel,apic-id = <0>;
35 intel,slow-ramp = <3>;
40 compatible = "intel,core-i3-gen5";
42 intel,apic-id = <1>;
47 compatible = "intel,core-i3-gen5";
[all …]
H A Dchromebook_link.dts1 /dts-v1/;
3 #include <dt-bindings/gpio/x86-gpio.h>
4 #include <dt-bindings/sound/azalia.h>
16 compatible = "google,link", "intel,celeron-ivybridge";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "intel,core-gen3";
36 intel,apic-id = <0>;
41 compatible = "intel,core-gen3";
43 intel,apic-id = <1>;
[all …]

12