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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Guenter Roeck <groeck@chromium.org>
14 Google's ChromeOS EC is a microcontroller which talks to the AP and
16 The EC can be connected through various interfaces (I2C, SPI, and others)
22 - description:
23 For implementations of the EC connected through I2C.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dgoogle,cros-ec-i2c-tunnel.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/i2c/google,cros-ec-i2c-tunnel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: I2C bus that tunnels through the ChromeOS EC (cros-ec)
11 - Doug Anderson <dianders@chromium.org>
12 - Benson Leung <bleung@chromium.org>
15 On some ChromeOS board designs we've got a connection to the EC
17 other side of the EC (like a battery and PMIC). To get access to
18 those devices we need to tunnel our i2c commands through the EC.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dgoogle,cros-ec-anx7688.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
10 - Nicolas Boichat <drinkcat@chromium.org>
13 ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
14 DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
16 (See google,cros-ec.yaml). It is accessed using I2C tunneling through
17 the EC and therefore its node should be a child of an EC I2C tunnel node
[all …]
/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dcros-ec.txt8 - compatible = "google,cros-ec"
11 - spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
13 - i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
15 - ec-interrupt : Selects the EC interrupt, defined as a GPIO according
17 - optimise-flash-write : Boolean property - if present then flash blocks
18 containing all 0xff will not be written, since we assume that the EC
22 to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
30 cros-ec@0 {
32 compatible = "google,cros-ec";
33 spi-max-frequency = <5000000>;
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/openbmc/linux/Documentation/devicetree/bindings/extcon/
H A Dextcon-usbc-cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/extcon/extcon-usbc-cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC USB Type-C cable and accessories detection
10 - Benson Leung <bleung@chromium.org>
16 The node for this device must be under a cros-ec node like google,cros-ec-spi
17 or google,cros-ec-i2c.
21 const: google,extcon-usbc-cros-ec
23 google,usb-port-id:
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 EC/H1 over SPI (common between IDP2 and CRD)
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
14 cros_ec: ec@0 {
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
[all …]
H A Dsc7280-herobrine.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
20 #include "sc7280-qcard.dtsi"
21 #include "sc7280-chrome-common.dtsi"
25 stdout-path = "serial0:115200n8";
38 ppvar_sys: ppvar-sys-regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "ppvar_sys";
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-cros-ec-tunnel.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Expose an I2C passthrough to the ChromeOS EC.
8 #include <linux/i2c.h>
17 * struct ec_i2c_device - Driver data for I2C tunnel
20 * @adap: I2C adapter
21 * @ec: Pointer to EC device
22 * @remote_bus: The EC bus number we tunnel to on the other side.
30 struct cros_ec_device *ec; member
39 * ec_i2c_count_message - Count bytes needed for ec_i2c_construct_message
41 * @i2c_msgs: The i2c messages to read
[all …]
/openbmc/u-boot/doc/device-tree-bindings/i2c/
H A Di2c.txt1 U-Boot I2C
2 ----------
4 U-Boot's I2C model has the concept of an offset within a chip (I2C target
9 Apart from the controller-specific I2C bindings, U-Boot supports a special
13 - u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the
15 - gpios = <sda ...>, <scl ...>;
16 pinctrl-names = "default", "gpio";
17 pinctrl-0 = <&i2c_xfer>;
18 pinctrl-1 = <&i2c_gpio>;
19 Pin description for I2C bus software deblocking.
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/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/rockchip,rk808.h>
10 #include <dt-bindings/input/input.h>
11 #include "rk3288-veyron.dtsi"
12 #include "rk3288-veyron-analog-audio.dtsi"
13 #include "rk3288-veyron-edp.dtsi"
14 #include "rk3288-veyron-sdmmc.dtsi"
22 gpio-charger {
23 compatible = "gpio-charger";
24 charger-type = "mains";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288-veyron.dtsi"
19 gpio_keys: gpio-keys {
20 pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
25 linux,input-type = <5>; /* EV_SW */
26 debounce-interval = <1>;
27 gpio-key,wakeup;
31 gpio-charger {
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H A Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
14 cpu-model = "Exynos5800";
16 compatible = "google,pit-rev#", "google,pit",
20 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
21 hwid = "PIT TEST A-A 7848";
22 lazy-init = <1>;
28 pmic = "/i2c@12CA0000";
33 compatible = "pwm-backlight";
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
[all …]
H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
11 #include <dt-bindings/clock/maxim,max77802.h>
12 #include <dt-bindings/regulator/maxim,max77802.h>
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
29 pmic = "/i2c@12CA0000";
[all …]
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
15 /* EC turns on w/ pp900_ap_en; always on for AP */
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
[all …]
H A Dexynos5250-snow.dts12 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/input/input.h>
23 i2c0 = "/i2c@12C60000";
24 i2c1 = "/i2c@12C70000";
25 i2c2 = "/i2c@12C80000";
26 i2c3 = "/i2c@12C90000";
27 i2c4 = "/i2c@12CA0000";
29 i2c5 = "/i2c@12CB0000";
[all …]
/openbmc/u-boot/include/
H A Dcros_ec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
20 struct gpio_desc ec_int; /* GPIO used as EC interrupt line */
25 * These two buffers will always be dword-aligned and include enough
26 * space for up to 7 word-alignment bytes also, so we can ensure that
27 * the body of the message is always dword-aligned (64-bit).
40 * Hard-code the number of columns we happen to know we have right now. It
51 /* Holds information about the Chrome EC */
53 struct fmap_entry flash; /* Address and size of EC flash */
55 * Byte value of erased flash, or -1 if not known. It is normally
63 * Read the ID of the CROS-EC device
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
46 ppvar_sys: ppvar-sys {
[all …]
/openbmc/linux/drivers/platform/chrome/
H A Dcros_ec_i2c.c1 // SPDX-License-Identifier: GPL-2.0
2 // I2C interface for ChromeOS Embedded Controller
10 #include <linux/i2c.h>
22 * byte 1-8 struct ec_host_request
23 * byte 10- response data
36 * byte 2-9 struct ec_host_response
37 * byte 10- response data
55 struct i2c_client *client = ec_dev->priv; in cros_ec_pkt_xfer_i2c()
56 int ret = -ENOMEM; in cros_ec_pkt_xfer_i2c()
69 i2c_msg[0].addr = client->addr; in cros_ec_pkt_xfer_i2c()
[all …]
/openbmc/u-boot/arch/sandbox/dts/
H A Dsandbox64.dts1 /dts-v1/;
6 #address-cells = <2>;
7 #size-cells = <2>;
17 stdout-path = "/serial";
20 cros_ec: cros-ec {
22 compatible = "google,cros-ec-sandbox";
25 * This describes the flash memory within the EC. Note
29 image-pos = <0x08000000>;
31 erase-value = <0>;
35 image-pos = <0>;
[all …]
H A Dsandbox.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
18 stdout-path = "/serial";
21 audio: audio-codec {
22 compatible = "sandbox,audio-codec";
23 #sound-dai-cells = <1>;
26 cros_ec: cros-ec {
28 u-boot,dm-pre-reloc;
29 compatible = "google,cros-ec-sandbox";
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dcros-ec-anx7688.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CrOS EC ANX7688 HDMI->DP bridge driver
10 #include <linux/i2c.h>
58 if (!anx->filter) in cros_ec_anx7688_bridge_mode_fixup()
62 ret = regmap_bulk_read(anx->regmap, ANX7688_DP_BANDWIDTH_REG, regs, 2); in cros_ec_anx7688_bridge_mode_fixup()
81 requiredbw = mode->clock * 8 * 3; in cros_ec_anx7688_bridge_mode_fixup()
100 struct device *dev = &client->dev; in cros_ec_anx7688_bridge_probe()
108 return -ENOMEM; in cros_ec_anx7688_bridge_probe()
110 anx7688->client = client; in cros_ec_anx7688_bridge_probe()
113 anx7688->regmap = devm_regmap_init_i2c(client, &cros_ec_anx7688_regmap_config); in cros_ec_anx7688_bridge_probe()
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
32 power-supply = <&ppvar_sys>;
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dcros_ec_proto.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 * The EC is unresponsive for a time after a reboot command. Add a
35 * Max bus-specific overhead incurred by request/responses.
36 * I2C requires 1 additional byte for requests.
37 * I2C requires 2 additional bytes for responses.
45 * EC panic is not covered by the standard (0-F) ACPI notify values.
46 * Arbitrarily choosing B0 to notify ec panic, which is in the 84-BF
52 * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
69 * struct cros_ec_command - Information about a ChromeOS EC command.
73 * @insize: Max number of bytes to accept from the EC.
[all …]
/openbmc/u-boot/drivers/misc/
H A Dcros_ec.c1 // SPDX-License-Identifier: GPL-2.0+
9 * This is the interface to the Chrome OS EC. It provides keyboard functions,
11 * provided to enable the EC software to be updated, talk to the EC's I2C bus
12 * and store a small amount of data in a memory which persists while the EC
21 #include <i2c.h>
28 #include <asm-generic/gpio.h>
29 #include <dm/device-internal.h>
31 #include <dm/uclass-internal.h>
49 * Map UHEPI masks to non UHEPI commands in order to support old EC FW
100 if (cmd != -1) in cros_ec_dump_data()
[all …]

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