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/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c18 * <http://www.gnu.org/licenses/gpl-2.0.html>
23 #include "cpu.h"
26 #include "hw/qdev-properties.h"
29 #include "cpu-features.h"
34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
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/openbmc/qemu/target/arm/hvf/
H A Dhvf.c8 * See the COPYING file in the top-level directory.
13 #include "qemu/error-report.h"
24 #include "exec/address-spaces.h"
27 #include "qemu/main-loop.h"
29 #include "arm-powerctl.h"
30 #include "target/arm/cpu.h"
185 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
186 #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)
187 #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0)
188 #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0)
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/openbmc/linux/Documentation/admin-guide/thermal/
H A Dintel_powerclamp.rst6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on…
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/openbmc/linux/Documentation/translations/zh_CN/mm/
H A Dmmu_notifier.rst28 - 上页表锁
29 - 清除页表项并通知 ([pmd/pte]p_huge_clear_flush_notify())
30 - 设置页表项以指向新页
37 两个地址addrA和addrB,这样|addrA - addrB| >= PAGE_SIZE,我们假设它们是COW的
42 [Time N] --------------------------------------------------------------------
43 CPU-thread-0 {尝试写到addrA}
44 CPU-thread-1 {尝试写到addrB}
45 CPU-thread-2 {}
46 CPU-thread-3 {}
47 DEV-thread-0 {读取addrA并填充设备TLB}
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/openbmc/linux/include/trace/events/
H A Dcpuhp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 TP_PROTO(unsigned int cpu,
17 TP_ARGS(cpu, target, idx, fun),
20 __field( unsigned int, cpu )
27 __entry->cpu = cpu;
28 __entry->target = target;
29 __entry->idx = idx;
30 __entry->fun = fun;
33 TP_printk("cpu: %04u target: %3d step: %3d (%ps)",
34 __entry->cpu, __entry->target, __entry->idx, __entry->fun)
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/openbmc/linux/Documentation/devicetree/bindings/
H A Dnuma.txt6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
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/openbmc/qemu/hw/misc/
H A Dallwinner-cpucfg.c2 * Allwinner CPU Configuration Module emulation
26 #include "qemu/error-report.h"
28 #include "hw/core/cpu.h"
29 #include "target/arm/arm-powerctl.h"
30 #include "target/arm/cpu.h"
31 #include "hw/misc/allwinner-cpucfg.h"
37 REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
38 REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
39 REG_CPU0_STATUS = 0x0048, /* CPU#0 Status */
40 REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
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/openbmc/linux/Documentation/mm/
H A Dmmu_notifier.rst8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
23 - take page table lock
24 - clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
25 - set page table entry to point to new page
33 Two address addrA and addrB such that \|addrA - addrB\| >= PAGE_SIZE we assume
38 [Time N] --------------------------------------------------------------------
39 CPU-thread-0 {try to write to addrA}
40 CPU-thread-1 {try to write to addrB}
41 CPU-thread-2 {}
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dextended.json3 "Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 "Unit": "CPU-M-CF",
21 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
24 "Unit": "CPU-M-CF",
28 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s…
31 "Unit": "CPU-M-CF",
35 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&power_key>;
25 power-key {
33 gpios = <&gpx0 3 GPIO_ACTIVE_LOW>;
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H A Dexynos5422-odroidhc1.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include "exynos5422-odroid-core.dtsi"
16 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
19 led-controller {
20 compatible = "pwm-leds";
22 led-1 {
26 pwm-names = "pwm2";
27 max-brightness = <255>;
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/openbmc/linux/kernel/
H A Dwatchdog_buddy.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/cpu.h>
7 #include <linux/percpu-defs.h>
11 static unsigned int watchdog_next_cpu(unsigned int cpu) in watchdog_next_cpu() argument
15 next_cpu = cpumask_next(cpu, &watchdog_cpus); in watchdog_next_cpu()
19 if (next_cpu == cpu) in watchdog_next_cpu()
30 void watchdog_hardlockup_enable(unsigned int cpu) in watchdog_hardlockup_enable() argument
35 * The new CPU will be marked online before the hrtimer interrupt in watchdog_hardlockup_enable()
36 * gets a chance to run on it. If another CPU tests for a in watchdog_hardlockup_enable()
37 * hardlockup on the new CPU before it has run its the hrtimer in watchdog_hardlockup_enable()
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/openbmc/qemu/target/arm/
H A Dkvm.c4 * Copyright Christoffer Dall 2009-2010
5 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
9 * See the COPYING file in the top-level directory.
19 #include "qemu/error-report.h"
20 #include "qemu/main-loop.h"
28 #include "cpu.h"
33 #include "exec/address-spaces.h"
54 * ARMHostCPUFeatures: information about the host CPU (identified
68 * @cpu: ARMCPU
71 * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature
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/openbmc/qemu/target/s390x/
H A Dioinst.c8 * your option) any later version. See the COPYING file in the top-level
14 #include "cpu.h"
15 #include "s390x-internal.h"
18 #include "hw/s390x/s390-pci-bus.h"
43 return -EINVAL; in ioinst_disassemble_sch_ident()
47 return -EINVAL; in ioinst_disassemble_sch_ident()
60 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra) in ioinst_handle_xsch() argument
66 s390_program_interrupt(&cpu->env, PGM_OPERAND, ra); in ioinst_handle_xsch()
72 setcc(cpu, 3); in ioinst_handle_xsch()
75 setcc(cpu, css_do_xsch(sch)); in ioinst_handle_xsch()
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/openbmc/qemu/docs/specs/
H A Dacpi_cpu_hotplug.rst1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
11 Legacy ACPI CPU hotplug interface registers
12 -------------------------------------------
14 CPU present bitmap for:
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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/openbmc/linux/Documentation/core-api/
H A Dworkqueue.rst32 worker thread per CPU and a single threaded (ST) wq had one worker
33 thread system-wide. A single MT wq needed to keep around the same
35 wq users over the years and with the number of CPU cores continuously
42 worker pool. An MT wq could provide only one execution context per CPU
60 * Use per-CPU unified worker pools shared by all wq to provide
83 called worker-pools.
85 The cmwq design differentiates between the user-facing workqueues that
87 which manages worker-pools and processes the queued work items.
89 There are two worker-pools, one for normal work items and the other
90 for high priority ones, for each possible CPU and some extra
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/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/dscr_default
2 Date: 13-May-2014
6 /sys/devices/system/cpu/cpuN/dscr on all CPUs.
9 all per-CPU defaults at the same time.
12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr
13 Date: 13-May-2014
17 a CPU.
22 on any CPU where it executes (overriding the value described
27 What: /sys/devices/system/cpu/cpuX/topology/physical_package_id
33 What: /sys/devices/system/cpu/cpuX/topology/die_id
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/openbmc/linux/Documentation/arch/x86/
H A Dtopology.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - cpuinfo_x86.x86_max_cores:
54 - cpuinfo_x86.x86_max_dies:
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/openbmc/linux/kernel/sched/
H A Dtopology.c1 // SPDX-License-Identifier: GPL-2.0
35 static int sched_domain_debug_one(struct sched_domain *sd, int cpu, int level, in sched_domain_debug_one() argument
38 struct sched_group *group = sd->groups; in sched_domain_debug_one()
39 unsigned long flags = sd->flags; in sched_domain_debug_one()
44 printk(KERN_DEBUG "%*s domain-%d: ", level, "", level); in sched_domain_debug_one()
46 cpumask_pr_args(sched_domain_span(sd)), sd->name); in sched_domain_debug_one()
48 if (!cpumask_test_cpu(cpu, sched_domain_span(sd))) { in sched_domain_debug_one()
49 printk(KERN_ERR "ERROR: domain->span does not contain CPU%d\n", cpu); in sched_domain_debug_one()
51 if (group && !cpumask_test_cpu(cpu, sched_group_span(group))) { in sched_domain_debug_one()
52 printk(KERN_ERR "ERROR: domain->groups does not contain CPU%d\n", cpu); in sched_domain_debug_one()
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/openbmc/linux/Documentation/tools/rtla/
H A Drtla-hwnoise.rst1 .. SPDX-License-Identifier: GPL-2.0
4 rtla-hwnoise
6 ------------------------------------------
7 Detect and quantify hardware-related noise
8 ------------------------------------------
22 of threads as a consequence, only non-maskable interrupts and hardware-related
38 In the example below, the **rtla hwnoise** tool is set to run on CPUs *1-7*
39 on a system with 8 cores/16 threads with hyper-threading enabled.
45 # rtla hwnoise -c 1-7 -T 1 -d 10m -q
46 Hardware-related Noise
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/openbmc/linux/tools/power/x86/intel_pstate_tracer/
H A Dintel_pstate_tracer.py2 # SPDX-License-Identifier: GPL-2.0-only
3 # -*- coding: utf-8 -*-
7 - If there is Linux trace file with pstate_sample events enabled, then
9 - If user has not specified a trace file as input via command line parameters,
16 gnuplot-py 1.8 or higher
18 gnuplot-py, phython-gnuplot or phython3-gnuplot, gnuplot-nox, ... )
20 HWP (Hardware P-States are disabled)
62 C_USEC = 3
79 print(' ./%s_tracer.py [-c cpus] -t <trace_file> -n <test_name>'%driver_name)
81 …print(' ./%s_tracer.py [--cpu cpus] ---trace_file <trace_file> --name <test_name>'%driver_nam…
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/openbmc/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dbooting.txt1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級(EL0 - EL3)組成,對於 EL0 和 EL1 異常級
45 這個術語來定義在將控制權交給 Linux 內核前 CPU 上執行的所有軟體。
53 3、解壓內核映像
58 -----------------
69 ---------------
80 3、解壓內核映像
81 -------------
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