/openbmc/linux/Documentation/devicetree/bindings/arm/ |
H A D | arm,coresight-tpiu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Arm CoreSight Trace Port Interface Unit 10 - Mathieu Poirier <mathieu.poirier@linaro.org> 11 - Mike Leach <mike.leach@linaro.org> 12 - Leo Yan <leo.yan@linaro.org> 13 - Suzuki K Poulose <suzuki.poulose@arm.com> 16 CoreSight components are compliant with the ARM CoreSight architecture [all …]
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/openbmc/linux/drivers/hwtracing/coresight/ |
H A D | coresight-tpiu.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 5 * Description: CoreSight Trace Port Interface Unit driver 16 #include <linux/coresight.h> 20 #include "coresight-priv.h" 43 /* FFSR - 0x300 */ 45 /* FFCR - 0x304 */ 50 DEFINE_CORESIGHT_DEVLIST(tpiu_devs, "tpiu"); 54 * @atclk: optional clock for the core parts of the TPIU. 65 CS_UNLOCK(csa->base); in tpiu_enable_hw() [all …]
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H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Coresight configuration 5 menuconfig CORESIGHT config 6 tristate "CoreSight Tracing Support" 13 This framework provides a kernel interface for the CoreSight debug 15 a topological view of the CoreSight components based on a DT 20 module will be called coresight. 22 if CORESIGHT 24 tristate "CoreSight Link and Sink drivers" 26 This enables support for CoreSight link and sink drivers that are [all …]
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H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 3 # Makefile for CoreSight drivers. 5 obj-$(CONFIG_CORESIGHT) += coresight.o 6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ 7 coresight-sysfs.o coresight-syscfg.o coresight-config.o \ 8 coresight-cfg-preload.o coresight-cfg-afdo.o \ 9 coresight-syscfg-configfs.o coresight-trace-id.o 10 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o 11 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ 12 coresight-tmc-etr.o [all …]
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/openbmc/linux/Documentation/trace/coresight/ |
H A D | coresight.rst | 2 Coresight - HW Assisted Tracing on ARM 9 ------------ 11 Coresight is an umbrella of technologies allowing for the debugging of ARM 24 flows through the coresight system (via ATB bus) using links that are connecting 25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight 28 host without fear of filling up the onboard coresight memory buffer. 30 At typical coresight system would look like this:: 38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System || 39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory || 40 | #######<-->: I : | #######<-->: I : : I : @@@<-| |||||||||||| [all …]
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/ |
H A D | hi6220-coresight.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * dtsi file for Hisilicon Hi6220 coresight 14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 17 clock-names = "apb_pclk"; 19 out-ports { 22 remote-endpoint = 28 in-ports { 31 remote-endpoint = 39 compatible = "arm,coresight-tmc", "arm,primecell"; 42 clock-names = "apb_pclk"; [all …]
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H A D | hi3660-coresight.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 * dtsi for Hisilicon Hi3660 Coresight 6 * Copyright (C) 2016-2018 HiSilicon Ltd. 15 compatible = "arm,coresight-etm4x", "arm,primecell"; 18 clock-names = "apb_pclk"; 21 out-ports { 24 remote-endpoint = 32 compatible = "arm,coresight-etm4x", "arm,primecell"; 35 clock-names = "apb_pclk"; 38 out-ports { [all …]
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/openbmc/linux/tools/perf/tests/shell/ |
H A D | test_arm_coresight.sh | 2 # Check Arm CoreSight trace data recording and synthesized samples 4 # Uses the 'perf record' to record trace data with Arm CoreSight sinks; 6 # are generated by CoreSight with 'perf script' and 'perf report' 9 # SPDX-License-Identifier: GPL-2.0 15 perf list | grep -q 'cs_etm//' && return 0 28 rm -f ${perfdata} 29 rm -f ${file} 30 rm -f "${perfdata}.old" 31 trap - EXIT TERM INT 39 rm -f $file [all …]
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/openbmc/linux/drivers/acpi/arm64/ |
H A D | amba.c | 1 // SPDX-License-Identifier: GPL-2.0-only 13 #include <linux/clk-provider.h> 24 {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */ 25 {"ARMHC501", 0}, /* ARM CoreSight ETR */ 26 {"ARMHC502", 0}, /* ARM CoreSight STM */ 27 {"ARMHC503", 0}, /* ARM CoreSight Debug */ 28 {"ARMHC979", 0}, /* ARM CoreSight TPIU */ 29 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */ 30 {"ARMHC98D", 0}, /* ARM CoreSight Dynamic Replicator */ 31 {"ARMHC9CA", 0}, /* ARM CoreSight CATU */ [all …]
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/openbmc/linux/arch/arm/boot/dts/hisilicon/ |
H A D | hip04.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013-2014 HiSilicon Ltd. 6 * Copyright (C) 2013-2014 Linaro Ltd. 12 /* memory bus is 64-bit */ 13 #address-cells = <2>; 14 #size-cells = <2>; 21 compatible = "hisilicon,hip04-bootwrapper"; 22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; 26 #address-cells = <1>; 27 #size-cells = <0>; [all …]
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca15_a7.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 * Cortex-A15_A7 MPCore (V2P-CA15_A7) 8 * HBI-0249A 11 /dts-v1/; 12 #include "vexpress-v2m-rs1.dtsi" 15 model = "V2P-CA15_CA7"; 18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; [all …]
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/openbmc/linux/arch/arm/boot/dts/xilinx/ |
H A D | zynq-7000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "xlnx,zynq-7000"; 12 #address-cells = <1>; 13 #size-cells = <0>; 16 compatible = "arm,cortex-a9"; 20 clock-latency = <1000>; 21 cpu0-supply = <®ulator_vccpint>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/arm/ |
H A D | juno-base.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include "juno-clocks.dtsi" 3 #include "juno-motherboard.dtsi" 11 compatible = "arm,armv7-timer-mem"; 13 clock-frequency = <50000000>; 14 #address-cells = <1>; 15 #size-cells = <1>; 19 frame-number = <1>; 31 #mbox-cells = <1>; 33 clock-names = "apb_pclk"; [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | msm8916.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 6 #include <dt-bindings/arm/coresight-cti-dt.h> 7 #include <dt-bindings/clock/qcom,gcc-msm8916.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/interconnect/qcom,msm8916.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/power/qcom-rpmpd.h> 12 #include <dt-bindings/reset/qcom,gcc-msm8916.h> 13 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | msm8996.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/qcom,gcc-msm8996.h> 8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/interconnect/qcom,msm8996.h> 11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/power/qcom-rpmpd.h> [all …]
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H A D | apq8016-sbc.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 6 /dts-v1/; 8 #include "msm8916-pm8916.dtsi" 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/leds/common.h> 12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 13 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> 14 #include <dt-bindings/sound/apq8016-lpass.h> 18 compatible = "qcom,apq8016-sbc", "qcom,apq8016"; [all …]
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/openbmc/qemu/hw/arm/ |
H A D | xilinx_zynq.c | 28 #include "hw/adc/zynq-xadc.h" 31 #include "qemu/error-report.h" 36 #include "hw/qdev-clock.h" 41 #include "target/arm/cpu-qom.h" 44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") 112 rom_add_blob_fixed("board-setup", board_setup_blob, in zynq_write_board_setup() 125 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); in gem_init() 144 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); in zynq_init_spi_flashes() 145 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); in zynq_init_spi_flashes() 146 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); in zynq_init_spi_flashes() [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx7s.dtsi | 5 * This file is dual-licensed: you can use it either under the terms 44 #include <dt-bindings/clock/imx7d-clock.h> 45 #include <dt-bindings/power/imx7-power.h> 46 #include <dt-bindings/gpio/gpio.h> 47 #include <dt-bindings/input/input.h> 48 #include <dt-bindings/interrupt-controller/arm-gic.h> 49 #include "imx7d-pinfunc.h" 52 #address-cells = <1>; 53 #size-cells = <1>; 56 * pre-existing /chosen node to be available to insert the [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx7s.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 6 #include <dt-bindings/clock/imx7d-clock.h> 7 #include <dt-bindings/power/imx7-power.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/reset/imx7-reset.h> 12 #include "imx7d-pinfunc.h" 15 #address-cells = <1>; 16 #size-cells = <1>; [all …]
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/openbmc/linux/arch/arm/boot/dts/st/ |
H A D | ste-dbx5x0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <dt-bindings/interrupt-controller/irq.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/clock/ste-db8500-clkout.h> 9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h> 10 #include <dt-bindings/mfd/dbx500-prcmu.h> 11 #include <dt-bindings/arm/ux500_pm_domains.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/thermal/thermal.h> 16 #address-cells = <1>; [all …]
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/openbmc/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-apq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/clock/qcom,gcc-msm8960.h> 5 #include <dt-bindings/clock/qcom,lcc-msm8960.h> 6 #include <dt-bindings/reset/qcom,gcc-msm8960.h> 7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/soc/qcom,gsbi.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> [all …]
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H A D | qcom-msm8974.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interconnect/qcom,msm8974.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/reset/qcom,gcc-msm8974.h> 10 #include <dt-bindings/gpio/gpio.h> 13 #address-cells = <1>; [all …]
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/openbmc/linux/ |
H A D | opengrok2.0.log | 1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms) 2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c' 3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms) 4 2024-1 [all...] |
H A D | opengrok0.0.log | 1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz' 2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz' 3 2024-12-2 [all...] |