| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/ |
| H A D | StorageControllerMetrics.v1_0_3.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
18 "number",
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
37 …"longDescription": "The object shall contain the NVMe-defined 'Endurance Group Critical Warning Su…
39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
45 "number",
54 …indication of whether namespaces in one or more Endurance Groups are in read-only mode not as a re…
[all …]
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| H A D | NetworkAdapter.v1_11_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
18 "number",
34 "description": "The available OEM-specific actions for this resource.",
35 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
42 "description": "The capabilities of a controller.",
43 "longDescription": "This type shall describe the capabilities of a controller.",
45 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
51 "number",
[all …]
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| H A D | StorageController.v1_9_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
16 …essed by a controller that reports this state for an ANA group provide non-optimized access charac…
17 …"Optimized": "Commands processed by a controller provide optimized access to any namespace in the …
24 … "description": "The ANA characteristics and volume information for a storage controller.",
25 …"This type shall contain the ANA characteristics and volume information for a storage controller.",
27 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
33 "number",
68 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
74 "number",
[all …]
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| H A D | GraphicsController.v1_0_2.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
18 "number",
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
36 …"description": "The `GraphicsController` schema defines a graphics controller that can be used to …
39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
45 "number",
54 "$ref": "http://redfish.dmtf.org/schemas/v1/odata-v4.json#/definitions/context"
[all …]
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| H A D | USBController.v1_0_1.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
18 "number",
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
37 …"longDescription": "This Redfish Specification-described type shall contain links to resources tha…
39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
45 "number",
56 …operties contained in this object shall conform to the Redfish Specification-described requirement…
[all …]
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| H A D | MediaController.v1_3_2.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
18 "number",
31 "description": "The available OEM-specific actions for this resource.",
32 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
40 …"longDescription": "This Redfish Specification-described type shall contain links to resources tha…
42 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
48 "number",
57 … "description": "An array of links to the endpoints that connect to this media controller.",
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci-msi.txt | 5 (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
6 Function number.
11 * Bits [15:8] are the Bus number.
12 * Bits [7:3] are the Device number.
13 * Bits [2:0] are the Function number.
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
[all …]
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| /openbmc/linux/Documentation/core-api/irq/ |
| H A D | irq-domain.rst | 2 The irq_domain interrupt number mapping library
5 The current design of the Linux kernel uses a single large number
6 space where each separate IRQ source is assigned a different number.
7 This is simple when there is only one interrupt controller, but in
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
18 Here the interrupt number loose all kind of correspondence to
21 interrupt controller (i.e. the component actually fireing the
22 interrupt line to the CPU) nowadays this number is just a number.
24 For this reason we need a mechanism to separate controller-local
[all …]
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| /openbmc/bmcweb/redfish-core/schema/oem/openbmc/json-schema/ |
| H A D | OpenBMCManager.v1_0_0.json | 2 …"$id": "https://github.com/openbmc/bmcweb/tree/master/redfish-core/schema/oem/openbmc/json-schema/…
3 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
11 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
17 "number",
87 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
93 "number",
105 "type": "number"
111 "type": "number"
117 "type": "number"
123 "type": "number"
[all …]
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| /openbmc/bmcweb/redfish-core/schema/dmtf/csdl/ |
| H A D | StorageControllerMetrics_v1.xml | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ …
4 <!--# Redfish Schema: StorageControllerMetrics v1.0.3 …
5 <!--# …
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, …
7 <!--# available at http://www.dmtf.org/standards/redfish …
8 <!--# Copyright 2014-2024 DMTF in cooperation with Storage Networking Industry Association (SNIA). …
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright …
10 <!--################################################################################ …
[all …]
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| /openbmc/qemu/docs/system/devices/ |
| H A D | nvme.rst | 5 QEMU provides NVMe emulation through the ``nvme``, ``nvme-ns`` and
6 ``nvme-subsys`` devices.
11 * Configuration of `Optional Features`_ such as `Controller Memory Buffer`_,
12 `Simple Copy`_, `Zoned Namespaces`_, `metadata`_ and `End-to-End Data
18 Controller Emulation
19 --------------------
21 The QEMU emulated NVMe controller implements version 1.4 of the NVM Express
29 The simplest way to attach an NVMe controller on the QEMU PCI bus is to add the
32 .. code-block:: console
34 -drive file=nvm.img,if=none,id=nvm
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.txt | 3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
4 controller. This binding document applies to both controllers. The register
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
11 package balls is under the control of a separate pin controller HW block. Two
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
36 The number of ports implemented by each GPIO controller varies. The number of
37 implemented GPIOs within each port varies. GPIO registers within a controller
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
[all …]
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| /openbmc/u-boot/lib/efi_selftest/ |
| H A D | efi_selftest_controllers.c | 1 // SPDX-License-Identifier: GPL-2.0+
37 * @count number of child controllers
49 ret = boottime->open_protocol_information(handle, protocol, in count_child_controllers()
56 if (entry_buffer[--entry_count].attributes & in count_child_controllers()
60 ret = boottime->free_pool(entry_buffer); in count_child_controllers()
67 * Check if the driver supports the controller.
70 * @controller_handle handle of the controller
71 * @remaining_device_path path specifying the child controller
82 ret = boottime->open_protocol( in supported()
95 ret = boottime->close_protocol( in supported()
[all …]
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/ |
| H A D | StorageController.v1_9_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
16 …essed by a controller that reports this state for an ANA group provide non-optimized access charac…
17 …"Optimized": "Commands processed by a controller provide optimized access to any namespace in the …
24 … "description": "The ANA characteristics and volume information for a storage controller.",
25 …"This type shall contain the ANA characteristics and volume information for a storage controller.",
27 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
33 "number",
68 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
74 "number",
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 By using a serial interface, the SIO controller significantly extend
14 the number of available GPIOs with a minimum number of additional
17 controller.
21 pattern: "^gpio@[0-9a-f]+$"
[all …]
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| /openbmc/linux/drivers/pinctrl/samsung/ |
| H A D | pinctrl-exynos-arm64.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
66 /* Must start with EINTG banks, ordered by EINT group number. */
78 /* pin banks of exynos5433 pin-controller - AUD */
80 /* Must start with EINTG banks, ordered by EINT group number. */
85 /* pin banks of exynos5433 pin-controller - CPIF */
[all …]
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| H A D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
71 * Samsung GPIO controller groups all the available pins into banks. The pins
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
118 * @pctl_offset: starting offset of the pin-bank registers.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
20 The Tegra186 GPIO controller allows software to set the IO direction of,
[all …]
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| H A D | gpio.txt | 5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
42 The exact meaning of each specifier cell is controller specific, and must be
44 recommended to use the two-cell approach.
[all …]
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| H A D | brcm,brcmstb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
7 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
17 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p…
27 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
36 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
45 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
54 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
59 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
63 …_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the to…
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/input/ |
| H A D | samsung-keypad.txt | 1 * Samsung's Keypad Controller device tree bindings
3 Samsung's Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
10 - compatible: should be one of the following
11 - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
12 controller.
13 - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
14 controller.
16 - reg: physical base address of the controller and length of memory mapped
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,omap2-intc.txt | 1 * OMAP Interrupt Controller
3 OMAP2/3 are using a TI interrupt controller that can support several
4 configurable number of interrupts.
8 - compatible : should be:
9 "ti,omap2-intc"
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
14 The cell contains the interrupt number in the range [0-128].
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
[all …]
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| H A D | ti,cp-intc.txt | 1 * TI Common Platform Interrupt Controller
3 Common Platform Interrupt Controller (cp_intc) is used on
4 OMAP-L1x SoCs and can support several configurable number
9 - compatible : should be:
10 "ti,cp-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
15 The cell contains the interrupt number in the range [0-128].
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
[all …]
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 9 This option, if enabled, provides more flexible and linux-like
19 bool "Support Atmel NAND controller"
23 controller.
36 The Programmable Multibit ECC (PMECC) controller is a programmable
64 bool "Support TI Davinci NAND controller"
75 bool "Support Denali NAND controller as a DT device"
80 controller as a DT device.
83 int "Number of bytes skipped in OOB area"
87 This option specifies the number of bytes to skip from the beginning
92 bool "Support LPC32XX_SLC controller"
[all …]
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