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1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V ISA extensions10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 RISC-V has a large number of extensions, some of which are "standard"16 extensions, meaning they are ratified by RISC-V International, and others36 Identifies the specific RISC-V instruction set architecture[all …]
2 * RISC-V Emulation Helpers for QEMU.4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu5 * Copyright (c) 2017-2018 SiFive, Inc.24 #include "exec/exec-all.h"26 #include "exec/helper-proto.h"33 cs->exception_index = exception; in riscv_raise_exception()45 * The seed CSR must be accessed with a read-write instruction. A in helper_csrr()46 * read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/ in helper_csrr()64 target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; in helper_csrw()93 env->retxh = int128_gethi(rv); in helper_csrr_i128()[all …]