| /openbmc/u-boot/drivers/adc/ |
| H A D | stm32-adc-core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
6 * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c.
12 #include "stm32-adc-core.h"
14 /* STM32H7 - common registers for all ADC instances */
17 /* STM32H7_ADC_CCR - bit fields */
23 /* STM32 H7 maximum analog clock rate (from datasheet) */
27 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
28 * @ckmode: ADC clock mode, Async or sync with prescaler.
29 * @presc: prescaler bitfield for async clock mode
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| /openbmc/linux/drivers/pwm/ |
| H A D | pwm-stm32-lp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer PWM driver
9 * Inspired by Gerald Baeza's pwm-stm32 driver
13 #include <linux/mfd/stm32-lptimer.h>
31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
40 u32 val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
47 if (!state->enabled) { in stm32_pwm_lp_apply()
50 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); in stm32_pwm_lp_apply()
53 /* disable clock to PWM counter */ in stm32_pwm_lp_apply()
54 clk_disable(priv->clk); in stm32_pwm_lp_apply()
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| /openbmc/linux/drivers/watchdog/ |
| H A D | stm32_iwdg.c | 1 // SPDX-License-Identifier: GPL-2.0
91 u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr; in stm32_iwdg_start() local
94 dev_dbg(wdd->parent, "%s\n", __func__); in stm32_iwdg_start()
96 tout = clamp_t(unsigned int, wdd->timeout, in stm32_iwdg_start()
97 wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000); in stm32_iwdg_start()
99 presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1); in stm32_iwdg_start()
102 presc = roundup_pow_of_two(presc); in stm32_iwdg_start()
103 iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT; in stm32_iwdg_start()
104 iwdg_rlr = ((tout * wdt->rate) / presc) - 1; in stm32_iwdg_start()
107 reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA); in stm32_iwdg_start()
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | stv6110.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
43 return a - b; in abssub()
45 return b - a; in abssub()
50 kfree(fe->tuner_priv); in stv6110_release()
51 fe->tuner_priv = NULL; in stv6110_release()
57 struct stv6110_priv *priv = fe->tuner_priv; in stv6110_write_regs()
61 .addr = priv->i2c_address, in stv6110_write_regs()
73 return -EINVAL; in stv6110_write_regs()
77 return -EINVAL; in stv6110_write_regs()
82 if (fe->ops.i2c_gate_ctrl) in stv6110_write_regs()
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| /openbmc/linux/drivers/iio/adc/ |
| H A D | stm32-adc-core.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
8 * Inspired from: fsl-imx25-tsadc
29 #include "stm32-adc-core.h"
45 * struct stm32_adc_common_regs - stm32 common registers
65 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
67 * @clk_sel: clock selection routine
68 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
85 * struct stm32_adc_priv - stm32 ADC core private data
89 * @aclk: clock reference for the analog circuitry
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| /openbmc/u-boot/drivers/i2c/ |
| H A D | stm32f7_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0+
130 * struct stm32_i2c_spec - private i2c specification timing
139 * @l_min: Min low period of the SCL clock (ns)
140 * @h_min: Min high period of the SCL clock (ns)
157 * struct stm32_i2c_setup - private I2C timing setup parameters
160 * @clock_src: I2C clock source frequency (Hz)
163 * @dnf: Digital filter coefficient (0-16)
177 * struct stm32_i2c_timings - private I2C output parameters
186 u8 presc; member
248 struct stm32_i2c_regs *regs = i2c_priv->regs; in stm32_i2c_check_device_busy()
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| /openbmc/linux/drivers/media/i2c/ |
| H A D | dw9768.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/v4l2-async.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
13 #include <media/v4l2-subdev.h>
16 #define DW9768_MAX_FOCUS_POS (1024 - 1)
56 * Bit[2:0] Namely PRESC[2:0], set the internal clock dividing rate as follow.
70 * Bit[5:0] Defined as VCM rising periodic time (Tvib) together with PRESC[2:0]
72 * Dividing Rate is the internal clock dividing rate that is defined at
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | dongwoon,dw9768.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Dongwoon DW9768 is a single 10-bit digital-to-analog (DAC) converter
16 a linear mode driver. The DAC is controlled via a 2-wire (I2C-compatible)
17 serial interface that operates at clock rates up to 1MHz. This chip
24 - dongwoon,dw9768 # for DW9768 VCM
25 - giantec,gt9769 # for GT9769 VCM
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| /openbmc/linux/drivers/i2c/busses/ |
| H A D | i2c-stm32f7.c | 1 // SPDX-License-Identifier: GPL-2.0
14 * This driver is based on i2c-stm32f4.c
21 #include <linux/i2c-smbus.h>
38 #include "i2c-stm32.h"
185 * struct stm32f7_i2c_regs - i2c f7 registers backup
201 * struct stm32f7_i2c_spec - private i2c specification timing
208 * @l_min: Min low period of the SCL clock (ns)
209 * @h_min: Min high period of the SCL clock (ns)
223 * struct stm32f7_i2c_setup - private I2C timing setup parameters
225 * @clock_src: I2C clock source frequency (Hz)
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| /openbmc/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
69 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
77 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
80 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
91 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
107 return -EINVAL; in enable_i2c_clk()
111 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
113 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-stm32-qspi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
93 #define STM32_AUTOSUSPEND_DELAY -1
97 u32 presc; member
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
141 complete(&qspi->match_completion); in stm32_qspi_irq()
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| /openbmc/u-boot/include/configs/ |
| H A D | socrates.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
119 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
122 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
138 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
147 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
160 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
193 /* I2C W83782G HW-Monitoring IC */
200 * Memory space is mapped 1-1.
241 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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