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/openbmc/linux/drivers/fpga/
H A Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
10 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
124 struct clk *clk; member
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
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H A Dsocfpga-a10.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Altera Corporation
7 #include <linux/clk.h>
10 #include <linux/fpga/fpga-mgr.h>
65 * struct a10_fpga_priv - private data for fpga manager
68 * @clk: clock
73 struct clk *clk; member
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
137 regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); in socfpga_a10_fpga_generate_dclks()
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/openbmc/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
17 - const: altr,clk-mgr
22 - compatible
27 - |
29 compatible = "altr,clk-mgr";
/openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dvenc.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
249 struct clk *tv_dac_clk;
273 venc_write_reg(VENC_LLEN, config->llen); in venc_write_config()
274 venc_write_reg(VENC_FLENS, config->flens); in venc_write_config()
275 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); in venc_write_config()
276 venc_write_reg(VENC_C_PHASE, config->c_phase); in venc_write_config()
277 venc_write_reg(VENC_GAIN_U, config->gain_u); in venc_write_config()
278 venc_write_reg(VENC_GAIN_V, config->gain_v); in venc_write_config()
279 venc_write_reg(VENC_GAIN_Y, config->gain_y); in venc_write_config()
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H A Ddss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
59 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
105 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
106 * Type-B PLLs: clkout[0] refers to m2.
152 struct clk *clkin;
210 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
212 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
214 int dss_mgr_check(struct omap_overlay_manager *mgr,
229 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
231 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
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H A Ddpi.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/clk.h>
55 /* only used in non-DT mode */
155 if (ctx->pck_min >= 100000000) { in dpi_calc_dispc_cb()
163 ctx->dispc_cinfo.lck_div = lckd; in dpi_calc_dispc_cb()
164 ctx->dispc_cinfo.pck_div = pckd; in dpi_calc_dispc_cb()
165 ctx->dispc_cinfo.lck = lck; in dpi_calc_dispc_cb()
166 ctx->dispc_cinfo.pck = pck; in dpi_calc_dispc_cb()
182 if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000) in dpi_calc_hsdiv_cb()
185 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dpi_calc_hsdiv_cb()
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H A Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
21 #include <linux/clk.h>
26 #include <sound/omap-hdmi-audio.h>
41 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
54 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
55 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
96 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
99 if (PTR_ERR(reg) != -EPROBE_DEFER) in hdmi_init_regulator()
146 struct omap_overlay_manager *mgr = hdmi.output.manager; in hdmi_power_on_full() local
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H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #include <linux/clk.h>
31 #include <sound/omap-hdmi-audio.h>
45 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
58 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
59 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
115 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
163 struct omap_overlay_manager *mgr = hdmi.output.manager; in hdmi_power_on_full() local
172 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
174 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
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H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk.h>
206 struct omap_overlay_manager *mgr);
208 struct omap_overlay_manager *mgr);
302 struct clk *dss_clk;
407 return to_platform_device(dssdev->dev); in dsi_get_dsidev_from_dssdev()
428 return out ? to_platform_device(out->dev) : NULL; in dsi_get_dsidev_from_id()
438 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
439 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
440 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
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/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 tick-timer = &timer2;
26 u-boot,dm-pre-reloc;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "altr,socfpga-a10-smp";
35 compatible = "arm,cortex-a9";
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H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53", "arm,armv8";
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/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
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H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Tali Perry <tali.perry1@gmail.com>
20 - nuvoton,npcm750-i2c
21 - nuvoton,npcm845-i2c
33 clock-frequency:
40 nuvoton,sys-mgr:
45 - compatible
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/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
40 static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk) in socfpga_a10_clk_get_upstream() argument
42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream()
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
54 dev_err(clk->dev, "Invalid control register\n"); in socfpga_a10_clk_get_upstream()
55 return -EINVAL; in socfpga_a10_clk_get_upstream()
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/openbmc/linux/include/video/
H A Domapfb_dss.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
88 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
91 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
92 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
93 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
94 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
99 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
100 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
101 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
102 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
[all …]
/openbmc/linux/drivers/clk/socfpga/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
14 #include "clk.h"
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
79 const char *clk_name = node->name; in __socfpga_pll_init()
91 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); in __socfpga_pll_init()
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H A Dclk-pll-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include "clk.h"
42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
72 const char *clk_name = node->name; in __socfpga_pll_init()
85 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); in __socfpga_pll_init()
89 pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; in __socfpga_pll_init()
91 of_property_read_string(node, "clock-output-names", &clk_name); in __socfpga_pll_init()
102 pll_clk->hw.hw.init = &init; in __socfpga_pll_init()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.h2 * Copyright 2012-16 Advanced Micro Devices, Inc.
34 /* functions shared with other clk mgr */
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.h2 * Copyright 2012-16 Advanced Micro Devices, Inc.
37 /* functions shared with other clk mgr*/
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-pltfm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/mfd/altera-sysmgr.h>
24 #include "dw_mmc-pltfm.h"
36 host = devm_kzalloc(&pdev->dev, sizeof(struct dw_mci), GFP_KERNEL); in dw_mci_pltfm_register()
38 return -ENOMEM; in dw_mci_pltfm_register()
40 host->irq = platform_get_irq(pdev, 0); in dw_mci_pltfm_register()
41 if (host->irq < 0) in dw_mci_pltfm_register()
42 return host->irq; in dw_mci_pltfm_register()
44 host->drv_data = drv_data; in dw_mci_pltfm_register()
45 host->dev = &pdev->dev; in dw_mci_pltfm_register()
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