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/openbmc/linux/drivers/phy/renesas/
H A Dr8a779f0-ether-serdes.c1 // SPDX-License-Identifier: GPL-2.0
18 #define R8A779F0_ETH_SERDES_OFFSET 0x0400
19 #define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc
37 struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM]; member
53 r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel, in r8a779f0_eth_serdes_reg_wait() argument
59 iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT); in r8a779f0_eth_serdes_reg_wait()
61 ret = readl_poll_timeout_atomic(channel->addr + offs, val, in r8a779f0_eth_serdes_reg_wait()
65 dev_dbg(&channel->phy->dev, in r8a779f0_eth_serdes_reg_wait()
67 __func__, channel->index, offs, bank, mask, expected); in r8a779f0_eth_serdes_reg_wait()
75 struct r8a779f0_eth_serdes_channel *channel; in r8a779f0_eth_serdes_common_init_ram() local
[all …]
/openbmc/linux/drivers/char/xillybus/
H A Dxillybus_core.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/dma-mapping.h>
43 #define fpga_msg_ctrl_reg 0x0008
44 #define fpga_dma_control_reg 0x0020
45 #define fpga_dma_bufno_reg 0x0024
46 #define fpga_dma_bufaddr_lowaddr_reg 0x0028
47 #define fpga_dma_bufaddr_highaddr_reg 0x002c
48 #define fpga_buf_ctrl_reg 0x0030
49 #define fpga_buf_offset_reg 0x0034
50 #define fpga_endian_reg 0x0040
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
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/openbmc/linux/drivers/net/ethernet/sfc/siena/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
35 * The default (0) means to assign an interrupt to each core.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
72 count = 0; in count_online_cores()
93 if (count == 0) in efx_wanted_parallelism()
98 netif_cond_dbg(efx, probe, efx->net_dev, !efx_siena_rss_cpus, in efx_wanted_parallelism()
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/openbmc/linux/drivers/net/ethernet/sfc/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
35 * The default (0) means to assign an interrupt to each core.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
72 count = 0; in count_online_cores()
93 if (count == 0) in efx_wanted_parallelism()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
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/openbmc/linux/drivers/staging/greybus/
H A Dlight.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/led-class-flash.h>
15 #include <media/v4l2-flash-led-class.h>
69 static void gb_lights_channel_free(struct gb_channel *channel);
71 static struct gb_connection *get_conn_from_channel(struct gb_channel *channel) in get_conn_from_channel() argument
73 return channel->light->glights->connection; in get_conn_from_channel()
78 return light->glights->connection; in get_conn_from_light()
81 static bool is_channel_flash(struct gb_channel *channel) in is_channel_flash() argument
83 return !!(channel->mode & (GB_CHANNEL_MODE_FLASH | GB_CHANNEL_MODE_TORCH in is_channel_flash()
95 static struct led_classdev *get_channel_cdev(struct gb_channel *channel) in get_channel_cdev() argument
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/openbmc/linux/drivers/ptp/
H A Dptp_clockmatrix.c1 // SPDX-License-Identifier: GPL-2.0+
27 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
33 * over-rides any automatic selection
36 module_param(firmware, charp, 0);
38 #define SETTIME_CORRECTION (0)
41 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
49 return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count); in idtcm_read()
58 return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count); in idtcm_write()
64 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data; in contains_full_configuration()
65 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); in contains_full_configuration()
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H A Dptp_idt82p33.c1 // SPDX-License-Identifier: GPL-2.0
25 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
34 module_param(phase_snap_threshold, uint, 0);
39 module_param(firmware, charp, 0);
46 return regmap_bulk_read(idt82p33->regmap, regaddr, buf, count); in idt82p33_read()
52 return regmap_bulk_write(idt82p33->regmap, regaddr, buf, count); in idt82p33_write()
63 for (i = 0; i < 3; i++) { in idt82p33_byte_array_to_timespec()
65 nsec |= buf[2 - i]; in idt82p33_byte_array_to_timespec()
69 for (i = 0; i < 5; i++) { in idt82p33_byte_array_to_timespec()
71 sec |= buf[8 - i]; in idt82p33_byte_array_to_timespec()
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/openbmc/linux/drivers/media/platform/allegro-dvt/
H A Dallegro-core.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/xlnx-vcu.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-event.h>
29 #include <media/v4l2-ioctl.h>
30 #include <media/v4l2-mem2mem.h>
31 #include <media/videobuf2-dma-contig.h>
32 #include <media/videobuf2-v4l2.h>
34 #include "allegro-mail.h"
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/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 #define QLA_MODEL_NAMES 0x5C
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
[all …]
/openbmc/linux/drivers/ipack/devices/
H A Dipoctal.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * driver for the GE IP-OCTAL boards
5 * Copyright (C) 2009-2012 CERN (www.cern.ch)
23 #define IP_OCTAL_ID_SPACE_VECTOR 0x41
48 struct ipoctal_channel channel[NR_CHANNELS]; member
57 return container_of(chan, struct ipoctal, channel[index]); in chan_to_ipoctal()
60 static void ipoctal_reset_channel(struct ipoctal_channel *channel) in ipoctal_reset_channel() argument
62 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
63 channel->rx_enable = 0; in ipoctal_reset_channel()
64 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr); in ipoctal_reset_channel()
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/openbmc/linux/drivers/dma/sh/
H A Drz-dmac.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on imx-dma.c
9 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
13 #include <linux/dma-mapping.h>
29 #include "../virt-dma.h"
108 * -----------------------------------------------------------------------------
112 #define CHSTAT 0x0024
113 #define CHCTRL 0x0028
114 #define CHCFG 0x002c
115 #define NXLA 0x0038
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/openbmc/linux/sound/soc/codecs/
H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
17 * Currently, the driver does not touch any of the registers >= 0x20, so
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
53 #define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */
55 #define TAS5086_CLOCK_RATE_MASK (0x7 << 5)
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/openbmc/linux/drivers/most/
H A Dmost_snd.c1 // SPDX-License-Identifier: GPL-2.0
3 * sound.c - Sound component for Mostcore
28 * struct channel - private structure to keep channel specific data
30 * @pcm_hardware: low-level hardware description
31 * @iface: interface for which the channel belongs to
32 * @cfg: channel configuration
35 * @id: channel index
42 * @copy_fn: copy function for PCM-specific format and width
44 struct channel { struct
79 unsigned int i = 0; in swap_copy16()
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/openbmc/phosphor-host-ipmid/user_channel/
H A Dchannel_layer.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
28 static constexpr uint8_t currentChNum = 0xE;
29 static constexpr uint8_t invalidChannel = 0xff;
30 static constexpr const uint8_t ccActionNotSupportedForChannel = 0x82;
31 static constexpr const uint8_t ccAccessModeNotSupportedForChannel = 0x83;
39 * @enum Channel Protocol Type (refer spec sec 6.4)
43 na = 0x00,
44 ipmbV10 = 0x01,
45 icmbV11 = 0x02,
46 reserved = 0x0
[all...]
/openbmc/linux/drivers/firmware/arm_scmi/
H A Doptee.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Linaro Ltd.
23 * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities
25 * [out] value[0].a: Capability bit mask (enum pta_scmi_caps)
26 * [out] value[0].b: Extended capabilities or 0
28 PTA_SCMI_CMD_CAPABILITIES = 0,
31 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL - Process SCMI message in SMT buffer
33 * [in] value[0].a: Channel handle
36 * already identified and bound to channel handle in both SCMI agent
37 * and SCMI server (OP-TEE) parts.
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/openbmc/linux/sound/xen/
H A Dxen_snd_front_evtchnl.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Xen para-virtual sound device
6 * Copyright (C) 2016-2018 EPAM Systems Inc.
23 struct xen_snd_front_evtchnl *channel = dev_id; in evtchnl_interrupt_req() local
24 struct xen_snd_front_info *front_info = channel->front_info; in evtchnl_interrupt_req()
28 if (unlikely(channel->state != EVTCHNL_STATE_CONNECTED)) in evtchnl_interrupt_req()
31 mutex_lock(&channel->ring_io_lock); in evtchnl_interrupt_req()
34 rp = channel->u.req.ring.sring->rsp_prod; in evtchnl_interrupt_req()
43 for (i = channel->u.req.ring.rsp_cons; i != rp; i++) { in evtchnl_interrupt_req()
44 resp = RING_GET_RESPONSE(&channel->u.req.ring, i); in evtchnl_interrupt_req()
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/openbmc/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define SSI_REVISION_REG 0
16 # define SSI_REV_MAJOR 0xf0
17 # define SSI_REV_MINOR 0xf
18 #define SSI_SYSCONFIG_REG 0x10
19 # define SSI_AUTOIDLE (1 << 0)
21 # define SSI_SIDLEMODE_FORCE 0
24 # define SSI_SIDLEMODE_MASK 0x18
25 # define SSI_MIDLEMODE_FORCE 0
28 # define SSI_MIDLEMODE_MASK 0x3000
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/openbmc/linux/drivers/rpmsg/
H A Dqcom_glink_native.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, Linaro Ltd
40 * struct glink_defer_cmd - deferred incoming control message
56 * struct glink_core_rx_intent - RX intent
59 * @data: pointer to the data (may be NULL for zero-copy)
63 * @in_use: To mark if intent is already in use for the channel
64 * @offset: next write offset (initially 0)
79 * struct qcom_glink - driver context, relates to one remote subsystem
88 * @lcids: idr of all channels with a known local channel id
89 * @rcids: idr of all channels with a known remote channel id
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H A Dqcom_smd.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
27 * The Qualcomm Shared Memory communication solution provides point-to-point
30 * Each channel consists of a control item (channel info) and a ring buffer
31 * pair. The channel info carry information related to channel state, flow
37 * Upon creating a new channel the remote processor allocates channel info and
39 * interrupt is sent to the other end of the channel and a scan for new
40 * channels should be done. A channel never goes away, it will only change
44 * channel by setting the state of its end of the channel to "opening" and
46 * consume the channel. Upon finding a consumer we finish the handshake and the
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/openbmc/linux/drivers/hsi/clients/
H A Dhsi_char.c1 // SPDX-License-Identifier: GPL-2.0-only
36 #define HSC_RXBREAK 0
42 #define HSC_CH_MASK 0xf
66 * struct hsc_channel - hsi_char internal channel data
67 * @ch: channel number
68 * @flags: Keeps state of the channel (open/close, reading, writing)
92 * struct hsc_client_data - hsi_char internal client data
112 static unsigned int max_data_size = 0x1000;
113 module_param(max_data_size, uint, 0);
116 static void hsc_add_tail(struct hsc_channel *channel, struct hsi_msg *msg, in hsc_add_tail() argument
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/openbmc/linux/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
17 #define MCDT_CH0_TXD 0x0
18 #define MCDT_CH0_RXD 0x28
19 #define MCDT_DAC0_WTMK 0x60
20 #define MCDT_ADC0_WTMK 0x88
21 #define MCDT_DMA_EN 0xb0
23 #define MCDT_INT_EN0 0xb4
24 #define MCDT_INT_EN1 0xb8
25 #define MCDT_INT_EN2 0xbc
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/openbmc/linux/arch/sh/drivers/dma/
H A Ddma-api.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/drivers/dma/dma-api.c
5 * SuperH-specific DMA management API
30 * the channel is. in get_dma_info()
33 if ((chan < info->first_vchannel_nr) || in get_dma_info()
34 (chan >= info->first_vchannel_nr + info->nr_channels)) in get_dma_info()
49 if (dmac_name && (strcmp(dmac_name, info->name) != 0)) in get_dma_info_by_name()
62 unsigned int nr = 0; in get_nr_channels()
68 nr += info->nr_channels; in get_nr_channels()
76 struct dma_channel *channel; in get_dma_channel() local
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/openbmc/u-boot/drivers/dma/
H A Dapbh_dma.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/dma.h>
22 #include <asm/mach-imx/regs-apbh.h>
27 * Test is the DMA channel is valid channel
29 int mxs_dma_validate_chan(int channel) in mxs_dma_validate_chan() argument
33 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) in mxs_dma_validate_chan()
34 return -EINVAL; in mxs_dma_validate_chan()
36 pchan = mxs_dma_channels + channel; in mxs_dma_validate_chan()
37 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) in mxs_dma_validate_chan()
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H A DMCD_dmaApi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 /*Main C file for multi-channel DMA API. */
15 /* This is an API-internal pointer to the DMA's registers */
26 * However, this (usually) gets relocated to on-chip SRAM, at which
34 * whether a DMA has ever been attempted on each channel, pausing
46 static void MCD_resmActions(int channel);
61 #define DBG_CTL_COMP1_TASK (0x00002000)
69 #define DBG_KILL_ALL_STAT (0xFFFFFFFF)
75 #define MCD_BYTE_SWAP_KILLER 0xFFF8888F
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