Home
last modified time | relevance | path

Searched +full:channel +full:- (Results 1 – 25 of 1064) sorted by relevance

12345678910>>...43

/openbmc/linux/drivers/net/ethernet/sfc/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
108 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
111 netif_warn(efx, probe, efx->net_dev, in efx_wanted_parallelism()
[all …]
/openbmc/linux/drivers/net/ethernet/sfc/siena/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !efx_siena_rss_cpus, in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
110 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
112 netif_warn(efx, probe, efx->net_dev, in efx_wanted_parallelism()
[all …]
/openbmc/linux/drivers/rpmsg/
H A Dqcom_smd.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
27 * The Qualcomm Shared Memory communication solution provides point-to-point
30 * Each channel consists of a control item (channel info) and a ring buffer
31 * pair. The channel info carry information related to channel state, flow
37 * Upon creating a new channel the remote processor allocates channel info and
39 * interrupt is sent to the other end of the channel and a scan for new
40 * channels should be done. A channel never goes away, it will only change
44 * channel by setting the state of its end of the channel to "opening" and
46 * consume the channel. Upon finding a consumer we finish the handshake and the
[all …]
H A Dqcom_glink_native.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, Linaro Ltd
40 * struct glink_defer_cmd - deferred incoming control message
56 * struct glink_core_rx_intent - RX intent
59 * @data: pointer to the data (may be NULL for zero-copy)
63 * @in_use: To mark if intent is already in use for the channel
79 * struct qcom_glink - driver context, relates to one remote subsystem
88 * @lcids: idr of all channels with a known local channel id
89 * @rcids: idr of all channels with a known remote channel id
128 * struct glink_channel - internal representation of a channel
[all …]
/openbmc/linux/drivers/char/xillybus/
H A Dxillybus_core.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/dma-mapping.h>
75 * register_mutex is endpoint-specific, and is held when non-atomic
87 * wr_mutex -> rd_mutex -> register_mutex -> wr_spinlock -> rd_spinlock
101 dev_warn(endpoint->dev, in malformed_message()
102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
108 * which is the natural case MSI and several other hardware-oriented
120 struct xilly_channel *channel; in xillybus_isr() local
122 buf = ep->msgbuf_addr; in xillybus_isr()
123 buf_size = ep->msg_buf_size/sizeof(u32); in xillybus_isr()
[all …]
/openbmc/linux/drivers/staging/greybus/
H A Dlight.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/led-class-flash.h>
15 #include <media/v4l2-flash-led-class.h>
69 static void gb_lights_channel_free(struct gb_channel *channel);
71 static struct gb_connection *get_conn_from_channel(struct gb_channel *channel) in get_conn_from_channel() argument
73 return channel->light->glights->connection; in get_conn_from_channel()
78 return light->glights->connection; in get_conn_from_light()
81 static bool is_channel_flash(struct gb_channel *channel) in is_channel_flash() argument
83 return !!(channel->mode & (GB_CHANNEL_MODE_FLASH | GB_CHANNEL_MODE_TORCH in is_channel_flash()
95 static struct led_classdev *get_channel_cdev(struct gb_channel *channel) in get_channel_cdev() argument
[all …]
/openbmc/linux/drivers/ipack/devices/
H A Dipoctal.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * driver for the GE IP-OCTAL boards
5 * Copyright (C) 2009-2012 CERN (www.cern.ch)
48 struct ipoctal_channel channel[NR_CHANNELS]; member
57 return container_of(chan, struct ipoctal, channel[index]); in chan_to_ipoctal()
60 static void ipoctal_reset_channel(struct ipoctal_channel *channel) in ipoctal_reset_channel() argument
62 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
63 channel->rx_enable = 0; in ipoctal_reset_channel()
64 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr); in ipoctal_reset_channel()
65 iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
[all …]
/openbmc/linux/drivers/phy/renesas/
H A Dr8a779f0-ether-serdes.c1 // SPDX-License-Identifier: GPL-2.0
37 struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM]; member
53 r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel, in r8a779f0_eth_serdes_reg_wait() argument
59 iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT); in r8a779f0_eth_serdes_reg_wait()
61 ret = readl_poll_timeout_atomic(channel->addr + offs, val, in r8a779f0_eth_serdes_reg_wait()
65 dev_dbg(&channel->phy->dev, in r8a779f0_eth_serdes_reg_wait()
67 __func__, channel->index, offs, bank, mask, expected); in r8a779f0_eth_serdes_reg_wait()
75 struct r8a779f0_eth_serdes_channel *channel; in r8a779f0_eth_serdes_common_init_ram() local
79 channel = &dd->channel[i]; in r8a779f0_eth_serdes_common_init_ram()
80 ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01); in r8a779f0_eth_serdes_common_init_ram()
[all …]
/openbmc/linux/drivers/dma/sh/
H A Drz-dmac.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on imx-dma.c
9 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
13 #include <linux/dma-mapping.h>
29 #include "../virt-dma.h"
108 * -----------------------------------------------------------------------------
171 * -----------------------------------------------------------------------------
178 writel(val, dmac->base + offset); in rz_dmac_writel()
184 writel(val, dmac->ext_base + offset); in rz_dmac_ext_writel()
189 return readl(dmac->ext_base + offset); in rz_dmac_ext_readl()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/openbmc/linux/drivers/media/platform/allegro-dvt/
H A Dallegro-core.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/xlnx-vcu.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-event.h>
29 #include <media/v4l2-ioctl.h>
30 #include <media/v4l2-mem2mem.h>
31 #include <media/videobuf2-dma-contig.h>
32 #include <media/videobuf2-v4l2.h>
34 #include "allegro-mail.h"
[all …]
/openbmc/linux/drivers/most/
H A Dmost_snd.c1 // SPDX-License-Identifier: GPL-2.0
3 * sound.c - Sound component for Mostcore
28 * struct channel - private structure to keep channel specific data
30 * @pcm_hardware: low-level hardware description
31 * @iface: interface for which the channel belongs to
32 * @cfg: channel configuration
35 * @id: channel index
42 * @copy_fn: copy function for PCM-specific format and width
44 struct channel { struct
93 while (i < bytes - 2) { in swap_copy24()
[all …]
/openbmc/linux/drivers/ptp/
H A Dptp_clockmatrix.c1 // SPDX-License-Identifier: GPL-2.0+
27 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
33 * over-rides any automatic selection
41 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
49 return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count); in idtcm_read()
58 return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count); in idtcm_write()
64 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data; in contains_full_configuration()
65 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); in contains_full_configuration()
73 full_count = (scratch - GPIO_USER_CONTROL) - in contains_full_configuration()
74 ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4; in contains_full_configuration()
[all …]
H A Dptp_idt82p33.c1 // SPDX-License-Identifier: GPL-2.0
25 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
46 return regmap_bulk_read(idt82p33->regmap, regaddr, buf, count); in idt82p33_read()
52 return regmap_bulk_write(idt82p33->regmap, regaddr, buf, count); in idt82p33_write()
65 nsec |= buf[2 - i]; in idt82p33_byte_array_to_timespec()
71 sec |= buf[8 - i]; in idt82p33_byte_array_to_timespec()
74 ts->tv_sec = sec; in idt82p33_byte_array_to_timespec()
75 ts->tv_nsec = nsec; in idt82p33_byte_array_to_timespec()
85 nsec = ts->tv_nsec; in idt82p33_timespec_to_byte_array()
86 sec = ts->tv_sec; in idt82p33_timespec_to_byte_array()
[all …]
/openbmc/phosphor-host-ipmid/user_channel/
H A Dchannelcommands.cpp8 // http://www.apache.org/licenses/LICENSE-2.0
21 #include <phosphor-logging/lg2.hpp>
28 /** @brief implements the set channel access command
29 * @ param ctx - context pointer
30 * @ param channel - channel number
31 * @ param reserved - skip 4 bits
32 * @ param accessMode - access mode for IPMI messaging
33 * @ param usrAuth - user level authentication (enable/disable)
34 * @ param msgAuth - per message authentication (enable/disable)
35 * @ param alertDisabled - PEF alerting (enable/disable)
[all …]
H A Dchannel_mgmt.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
19 #include "ipmid/api-types.hpp"
45 * Structure to store both non-volatile and volatile channel access information
56 * Structure for channel information - base structure to get all information
57 * about the channel.(refer spec sec 22.22 to 22.24)
86 /** @brief determines valid channel
88 * @param[in] chNum - channel number
96 * @param[in] chNum - channel number
97 * @param[in] authType - authentication type
103 /** @brief function to get channel name from channel number
[all …]
/openbmc/linux/drivers/hsi/clients/
H A Dhsi_char.c1 // SPDX-License-Identifier: GPL-2.0-only
66 * struct hsc_channel - hsi_char internal channel data
67 * @ch: channel number
68 * @flags: Keeps state of the channel (open/close, reading, writing)
92 * struct hsc_client_data - hsi_char internal client data
116 static void hsc_add_tail(struct hsc_channel *channel, struct hsi_msg *msg, in hsc_add_tail() argument
121 spin_lock_irqsave(&channel->lock, flags); in hsc_add_tail()
122 list_add_tail(&msg->link, queue); in hsc_add_tail()
123 spin_unlock_irqrestore(&channel->lock, flags); in hsc_add_tail()
126 static struct hsi_msg *hsc_get_first_msg(struct hsc_channel *channel, in hsc_get_first_msg() argument
[all …]
/openbmc/linux/sound/xen/
H A Dxen_snd_front_evtchnl.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Xen para-virtual sound device
6 * Copyright (C) 2016-2018 EPAM Systems Inc.
23 struct xen_snd_front_evtchnl *channel = dev_id; in evtchnl_interrupt_req() local
24 struct xen_snd_front_info *front_info = channel->front_info; in evtchnl_interrupt_req()
28 if (unlikely(channel->state != EVTCHNL_STATE_CONNECTED)) in evtchnl_interrupt_req()
31 mutex_lock(&channel->ring_io_lock); in evtchnl_interrupt_req()
34 rp = channel->u.req.ring.sring->rsp_prod; in evtchnl_interrupt_req()
43 for (i = channel->u.req.ring.rsp_cons; i != rp; i++) { in evtchnl_interrupt_req()
44 resp = RING_GET_RESPONSE(&channel->u.req.ring, i); in evtchnl_interrupt_req()
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
[all …]
/openbmc/linux/drivers/gpu/host1x/
H A Dchannel.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Tegra host1x Channel
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
11 #include "channel.h"
19 chlist->channels = kcalloc(num_channels, sizeof(struct host1x_channel), in host1x_channel_list_init()
21 if (!chlist->channels) in host1x_channel_list_init()
22 return -ENOMEM; in host1x_channel_list_init()
24 chlist->allocated_channels = bitmap_zalloc(num_channels, GFP_KERNEL); in host1x_channel_list_init()
25 if (!chlist->allocated_channels) { in host1x_channel_list_init()
26 kfree(chlist->channels); in host1x_channel_list_init()
[all …]
/openbmc/u-boot/drivers/dma/
H A Dapbh_dma.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/dma.h>
22 #include <asm/mach-imx/regs-apbh.h>
27 * Test is the DMA channel is valid channel
29 int mxs_dma_validate_chan(int channel) in mxs_dma_validate_chan() argument
33 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) in mxs_dma_validate_chan()
34 return -EINVAL; in mxs_dma_validate_chan()
36 pchan = mxs_dma_channels + channel; in mxs_dma_validate_chan()
37 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) in mxs_dma_validate_chan()
[all …]
/openbmc/linux/drivers/firmware/arm_scmi/
H A Doptee.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Linaro Ltd.
23 * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities
31 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL - Process SCMI message in SMT buffer
33 * [in] value[0].a: Channel handle
36 * already identified and bound to channel handle in both SCMI agent
37 * and SCMI server (OP-TEE) parts.
38 * The memory uses SMT header to carry SCMI meta-data (protocol ID and
44 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE - Process SMT/SCMI message
46 * [in] value[0].a: Channel handle
[all …]
/openbmc/linux/drivers/net/ipa/
H A Dgsi.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2023 Linaro Ltd.
31 * providing a well-defined communication layer between the AP subsystem
34 * -------- ---------
36 * | AP +<---. .----+ Modem |
37 * | +--. | | .->+ |
39 * -------- | | | | ---------
41 * --+-+---+-+--
43 * |-----------|
[all …]
/openbmc/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_imem_ops.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
15 /* Open a packet data online channel between the network layer and CP. */
18 dev_dbg(ipc_imem->dev, "%s if id: %d", in ipc_imem_sys_wwan_open()
19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
23 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id, in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
25 return -EIO; in ipc_imem_sys_wwan_open()
28 return ipc_mux_open_session(ipc_imem->mux, if_id); in ipc_imem_sys_wwan_open()
35 if (ipc_imem->mux && if_id >= IP_MUX_SESSION_START && in ipc_imem_sys_wwan_close()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
71 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
89 * Default TAS5086 power-up configuration
173 size = tas5086_register_size(&client->dev, reg); in tas5086_reg_write()
[all …]

12345678910>>...43