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/openbmc/linux/drivers/i2c/busses/
H A Di2c-qcom-cci.c108 struct cci;
116 struct cci *cci; member
127 struct cci { struct
139 struct cci *cci = dev; in cci_isr() argument
143 val = readl(cci->base + CCI_IRQ_STATUS_0); in cci_isr()
144 writel(val, cci->base + CCI_IRQ_CLEAR_0); in cci_isr()
145 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); in cci_isr()
148 complete(&cci->master[0].irq_complete); in cci_isr()
149 if (cci->master[1].master) in cci_isr()
150 complete(&cci->master[1].irq_complete); in cci_isr()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
7 title: ARM CCI Cache Coherent Interconnect
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
35 Specifies base physical address of CCI control registers common to all
48 const: arm,cci-400-ctrl-if
71 - const: arm,cci-400-pmu,r0
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H A Dcci-control-port.yaml4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
19 cci-control-port:
33 cci-control-port = <&cci_control1>;
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dqcom,i2c-cci.yaml4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
7 title: Qualcomm Camera Control Interface (CCI) I2C controller
17 - qcom,msm8226-cci
18 - qcom,msm8974-cci
19 - qcom,msm8996-cci
23 - qcom,msm8916-cci
24 - const: qcom,msm8226-cci # CCI v1
28 - qcom,sdm845-cci
29 - qcom,sm6350-cci
30 - qcom,sm8250-cci
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/openbmc/qemu/hw/cxl/
H A Dcxl-mailbox-utils.c108 /* CCI Message Format CXL r3.1 Figure 7-19 */
129 CXLCCI *cci) in cmd_tunnel_management_cmd() argument
176 * Target of a tunnel unfortunately depends on type of CCI readint in cmd_tunnel_management_cmd()
182 if (object_dynamic_cast(OBJECT(cci->d), TYPE_CXL_TYPE3)) { in cmd_tunnel_management_cmd()
183 CXLType3Dev *ct3d = CXL_TYPE3(cci->d); in cmd_tunnel_management_cmd()
189 } else if (object_dynamic_cast(OBJECT(cci->d), TYPE_CXL_USP)) { in cmd_tunnel_management_cmd()
190 CXLUpstreamPort *usp = CXL_USP(cci->d); in cmd_tunnel_management_cmd()
221 /* Payload should be in place. Rest of CCI header and needs filling */ in cmd_tunnel_management_cmd()
237 CXLCCI *cci) in cmd_events_get_records() argument
239 CXLDeviceState *cxlds = &CXL_TYPE3(cci->d)->cxl_dstate; in cmd_events_get_records()
[all …]
H A Dcxl-device-utils.c66 CXLCCI *cci = opaque; in mailbox_reg_read() local
68 if (object_dynamic_cast(OBJECT(cci->intf), TYPE_CXL_TYPE3)) { in mailbox_reg_read()
69 cxl_dstate = &CXL_TYPE3(cci->intf)->cxl_dstate; in mailbox_reg_read()
70 } else if (object_dynamic_cast(OBJECT(cci->intf), in mailbox_reg_read()
72 cxl_dstate = &CXL_SWITCH_MAILBOX_CCI(cci->intf)->cxl_dstate; in mailbox_reg_read()
88 cci->bg.opcode); in mailbox_reg_read()
90 PERCENTAGE_COMP, cci->bg.complete_pct); in mailbox_reg_read()
92 RET_CODE, cci->bg.ret_code); in mailbox_reg_read()
98 if (cci->bg.complete_pct) { in mailbox_reg_read()
155 CXLCCI *cci = opaque; in mailbox_reg_write() local
[all …]
H A Dswitch-mailbox-cci.c4 * Emulation of a CXL Switch Mailbox CCI PCIe function.
43 cswmb->cci = &usp->swcci; in cswbcci_realize()
44 cxl_device_register_block_init(OBJECT(pci_dev), cxl_dstate, cswmb->cci); in cswbcci_realize()
58 cxl_initialize_mailbox_swcci(cswmb->cci, DEVICE(pci_dev), in cswbcci_realize()
81 /* Serial bus, CXL Switch CCI */ in cswmbcci_class_init()
85 * CXL Switch Mailbox CCI - DID assigned for emulation only. in cswmbcci_class_init()
91 dc->desc = "CXL Switch Mailbox CCI"; in cswmbcci_class_init()
/openbmc/linux/drivers/bus/
H A Darm-cci.c2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
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/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dmediatek,cci.yaml4 $id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
35 - const: cci
44 Phandle of the regulator for CCI that provides the supply voltage.
48 Phandle of the regulator for sram of CCI that provides the supply
66 cci: cci {
67 compatible = "mediatek,mt8183-cci";
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/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dsoc.c111 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + in erratum_a008850_early() local
116 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); in erratum_a008850_early()
127 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + in erratum_a008850_post() local
133 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); in erratum_a008850_post()
162 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + in arch_soc_init() local
185 out_le32(&cci->slave[0].snoop_ctrl, in arch_soc_init()
187 out_le32(&cci->slave[1].snoop_ctrl, in arch_soc_init()
189 out_le32(&cci->slave[2].snoop_ctrl, in arch_soc_init()
191 out_le32(&cci->slave[4].snoop_ctrl, in arch_soc_init()
197 * Set CCI-400 Slave interface S1, S2 Shareable Override in arch_soc_init()
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/openbmc/linux/drivers/usb/typec/ucsi/
H A Dtrace.c36 const char *ucsi_cci_str(u32 cci) in ucsi_cci_str() argument
38 if (UCSI_CCI_CONNECTOR(cci)) { in ucsi_cci_str()
39 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
41 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
45 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
47 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
H A Ducsi_acpi.c195 u32 cci; in ucsi_acpi_notify() local
198 ret = ua->ucsi->ops->read(ua->ucsi, UCSI_CCI, &cci, sizeof(cci)); in ucsi_acpi_notify()
202 if (UCSI_CCI_CONNECTOR(cci) && in ucsi_acpi_notify()
204 ucsi_connector_change(ua->ucsi, UCSI_CCI_CONNECTOR(cci)); in ucsi_acpi_notify()
206 if (cci & UCSI_CCI_ACK_COMPLETE && test_bit(ACK_PENDING, &ua->flags)) in ucsi_acpi_notify()
208 if (cci & UCSI_CCI_COMMAND_COMPLETE && in ucsi_acpi_notify()
H A Ducsi.c131 u32 cci; in ucsi_exec_command() local
138 ret = ucsi->ops->read(ucsi, UCSI_CCI, &cci, sizeof(cci)); in ucsi_exec_command()
142 if (cmd != UCSI_CANCEL && cci & UCSI_CCI_BUSY) in ucsi_exec_command()
145 if (!(cci & UCSI_CCI_COMMAND_COMPLETE)) in ucsi_exec_command()
148 if (cci & UCSI_CCI_NOT_SUPPORTED) { in ucsi_exec_command()
155 if (cci & UCSI_CCI_ERROR) { in ucsi_exec_command()
166 if (cmd == UCSI_CANCEL && cci & UCSI_CCI_CANCEL_COMPLETE) { in ucsi_exec_command()
171 return UCSI_CCI_LENGTH(cci); in ucsi_exec_command()
990 u32 cci; in ucsi_reset_ppm() local
995 ret = ucsi->ops->read(ucsi, UCSI_CCI, &cci, sizeof(cci)); in ucsi_reset_ppm()
[all …]
/openbmc/linux/drivers/perf/
H A DKconfig10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
35 internal events to the CCI.
H A Darm-cci.c2 // CCI Cache Coherent Interconnect PMU driver
6 #include <linux/arm-cci.h>
16 #define DRIVER_NAME "ARM-CCI PMU"
162 * Instead of an event id to monitor CCI cycles, a dedicated counter is
163 * provided. Use 0xff to represent CCI cycles and hope that no future revisions
174 * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
635 * Program the CCI PMU counters which have PERF_HES_ARCH set
749 * For all counters on the CCI-PMU, disable any 'enabled' counters,
788 * by the cci
834 dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); in pmu_request_irq()
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/openbmc/linux/arch/ia64/kernel/
H A Dtopology.c110 pal_cache_config_info_t cci; member
173 return sprintf(buf, "%u\n", 1 << this_leaf->cci.pcci_line_size); in show_coherency_line_size()
179 return sprintf(buf, "%u\n", this_leaf->cci.pcci_assoc); in show_ways_of_associativity()
186 cache_mattrib[this_leaf->cci.pcci_cache_attr]); in show_attributes()
191 return sprintf(buf, "%uK\n", this_leaf->cci.pcci_cache_size / 1024); in show_size()
196 unsigned number_of_sets = this_leaf->cci.pcci_cache_size; in show_number_of_sets()
197 number_of_sets /= this_leaf->cci.pcci_assoc; in show_number_of_sets()
198 number_of_sets /= 1 << this_leaf->cci.pcci_line_size; in show_number_of_sets()
215 int type = this_leaf->type + this_leaf->cci.pcci_unified; in show_type()
297 pal_cache_config_info_t cci; in cpu_cache_sysfs_init() local
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H A Dpalinfo.c215 pal_cache_config_info_t cci; in cache_info() local
230 if ((status=ia64_pal_cache_config_info(i,j, &cci)) != 0) in cache_info()
237 cache_types[j+cci.pcci_unified], i+1, in cache_info()
238 cci.pcci_cache_size); in cache_info()
240 if (cci.pcci_unified) in cache_info()
243 seq_printf(m, "%s\n", cache_mattrib[cci.pcci_cache_attr]); in cache_info()
249 cci.pcci_assoc, in cache_info()
250 1<<cci.pcci_line_size, in cache_info()
251 1<<cci.pcci_stride); in cache_info()
256 cci.pcci_st_latency); in cache_info()
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420-cpus.dtsi63 cci-control-port = <&cci_control1>;
75 cci-control-port = <&cci_control1>;
87 cci-control-port = <&cci_control1>;
99 cci-control-port = <&cci_control1>;
111 cci-control-port = <&cci_control0>;
123 cci-control-port = <&cci_control0>;
135 cci-control-port = <&cci_control0>;
147 cci-control-port = <&cci_control0>;
H A Dexynos5422-cpus.dtsi62 cci-control-port = <&cci_control0>;
75 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
101 cci-control-port = <&cci_control0>;
114 cci-control-port = <&cci_control1>;
127 cci-control-port = <&cci_control1>;
140 cci-control-port = <&cci_control1>;
153 cci-control-port = <&cci_control1>;
H A Dexynos5260.dtsi67 cci-control-port = <&cci_control1>;
74 cci-control-port = <&cci_control1>;
81 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
95 cci-control-port = <&cci_control0>;
102 cci-control-port = <&cci_control0>;
355 cci: cci@10f00000 { label
356 compatible = "arm,cci-400";
363 compatible = "arm,cci-400-ctrl-if";
369 compatible = "arm,cci-400-ctrl-if";
/openbmc/u-boot/board/armltd/vexpress/
H A Dvexpress_tc2.c43 const char *cci_compatible = "arm,cci-400-ctrl-if"; in ft_board_setup()
51 /* Booting in nonsec mode, disable CCI access */ in ft_board_setup()
58 /* delete cci-control-port in each cpu node */ in ft_board_setup()
61 fdt_delprop(fdt, tmp, "cci-control-port"); in ft_board_setup()
63 /* disable all ace cci slave ports */ in ft_board_setup()
/openbmc/qemu/include/hw/cxl/
H A Dcxl_device.h142 CXLCCI *cci);
200 /* Pointer to device hosting the CCI */
262 CXLCCI *cci);
315 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max);
316 void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf,
318 void cxl_init_cci(CXLCCI *cci, size_t payload_max);
319 void cxl_add_cci_commands(CXLCCI *cci, const struct cxl_cmd (*cxl_cmd_set)[256],
321 int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
325 void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d,
329 void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d,
[all …]
/openbmc/linux/drivers/devfreq/
H A Dmtk-cci-devfreq.c172 /* switch the cci clock to intermediate clock source. */ in mtk_ccifreq_target()
175 dev_err(dev, "failed to re-parent cci clock\n"); in mtk_ccifreq_target()
182 dev_err(dev, "failed to set cci pll rate: %d\n", ret); in mtk_ccifreq_target()
187 /* switch the cci clock back to the original clock source. */ in mtk_ccifreq_target()
190 dev_err(dev, "failed to re-parent cci clock\n"); in mtk_ccifreq_target()
267 drv->cci_clk = devm_clk_get(dev, "cci"); in mtk_ccifreq_probe()
270 return dev_err_probe(dev, ret, "failed to get cci clk\n"); in mtk_ccifreq_probe()
426 { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
427 { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
442 MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt23 - mediatek,cci:
24 Used to confirm the link status between cpufreq and mediatek cci. Because
25 cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
27 property to make sure mediatek cci is ready.
28 For details of mediatek cci, please refer to
29 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
/openbmc/linux/include/media/
H A Dv4l2-cci.h3 * MIPI Camera Control Interface (CCI) register access helpers.
18 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
54 * cci_read() - Read a value from a single CCI register
67 * cci_write() - Write a value to a single CCI register
81 * a single CCI register

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