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/openbmc/linux/include/linux/comedi/
H A Dcomedi_8254.h66 * @osc_base: cascaded oscillator speed in ns
68 * @divisor1: divisor loaded into first cascaded counter
69 * @divisor2: divisor loaded into second cascaded counter
71 * @next_div1: next divisor to use for first cascaded counter
72 * @next_div2: next divisor to use for second cascaded counter
/openbmc/linux/drivers/gpio/
H A Dgpio-exar.c41 * The offset to the cascaded device's (if existing)
51 unsigned int cascaded = offset / 16; in exar_offset_to_sel_addr() local
54 return addr + (cascaded ? exar_gpio->cascaded_offset : 0); in exar_offset_to_sel_addr()
61 unsigned int cascaded = offset / 16; in exar_offset_to_lvl_addr() local
64 return addr + (cascaded ? exar_gpio->cascaded_offset : 0); in exar_offset_to_lvl_addr()
179 * If cascaded, secondary xr17v354 or xr17v358 have the same amount in gpio_exar_probe()
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dtwl-family.txt17 it is considered as an interrupt controller cascaded to the SoC one.
34 interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
H A Dtwl4030-audio.txt32 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
H A Dtwl4030-power.txt40 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
/openbmc/linux/drivers/comedi/drivers/
H A Dcomedi_8254.c75 * provided to handle the cascaded counters:
89 * Programs the mode of the cascaded counters and writes the current
100 * counters that are used for the cascaded 32-bit pacer.
296 * comedi_8254_pacer_enable - set the mode and load the cascaded counters
333 * comedi_8254_update_divisors - update the divisors for the cascaded counters
346 * comedi_8254_cascade_ns_to_timer - calculate the cascaded divisor values
/openbmc/linux/arch/powerpc/platforms/52xx/
H A Dmedia5200.c13 * a cascaded interrupt controller driver which attaches itself to the
85 /* Mask off the cascaded IRQ */ in media5200_irq_cascade()
164 pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq); in media5200_init_irq()
/openbmc/linux/arch/m68k/include/asm/
H A Dmacints.h106 /* Nubus interrupts (cascaded to VIA2) */
115 /* Baboon interrupts (cascaded to nubus slot $C) */
/openbmc/u-boot/arch/x86/lib/
H A Di8259.c12 * based on the standard PC/AT architecture using two cascaded i8259
55 * Enable cascaded interrupts by unmasking the cascade IRQ pin of in i8259_init()
/openbmc/linux/arch/powerpc/platforms/powermac/
H A Dpic.c302 /* We might have a second cascaded ohare */ in pmac_pic_probe_oldstyle()
309 /* We might have a second cascaded heathrow */ in pmac_pic_probe_oldstyle()
351 /* Map interrupts of cascaded controller */ in pmac_pic_probe_oldstyle()
476 /* We can have up to 2 MPICs cascaded */ in pmac_pic_probe_mpic()
510 /* Set up a cascaded controller, if present */ in pmac_pic_probe_mpic()
/openbmc/linux/Documentation/driver-api/gpio/
H A Ddriver.rst258 most often cascaded off a parent interrupt controller, and in some special
280 - CASCADED INTERRUPT CHIPS: this means that the GPIO chip has one common
309 Cascaded GPIO irqchips
312 Cascaded GPIO irqchips usually fall in one of three categories:
314 - CHAINED CASCADED GPIO IRQCHIPS: these are usually the type that is embedded on
419 is a typical example of a chained cascaded interrupt handler using
665 is cascaded, set the handler to handle_level_irq() and/or handle_edge_irq()
/openbmc/linux/arch/xtensa/platforms/xt2000/include/platform/
H A Dhardware.h31 /* The XT2000 uses the V3 as a cascaded interrupt controller for the PCI bus */
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-duovero.dtsi168 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
175 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
H A Domap4-var-som-om44.dtsi176 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
188 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
H A Domap2430-sdp.dts24 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,versatile-fpga-irq.txt36 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
H A Dnxp,lpc3220-mic.txt17 - interrupts: empty for MIC interrupt controller, cascaded MIC
/openbmc/linux/drivers/irqchip/
H A Dirq-bcm2835.c18 * In a proper cascaded interrupt controller, the interrupt lines with
19 * cascaded interrupt controllers on them are just normal interrupt lines.
H A Dirq-goldfish-pic.c20 /* 8..39 Cascaded Goldfish PIC interrupts */
/openbmc/linux/arch/hexagon/kernel/
H A Dirq_cpu.c58 * controllers that are cascaded into one or more of the first-level
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A D8xxx_gpio.txt16 The GPIO module may serve as another interrupt controller (cascaded to
/openbmc/openbmc/poky/meta/lib/oeqa/selftest/cases/
H A Dfitimage.py604 a_comment = "a smart cascaded U-Boot comment"
614 SPL_SIGN_KEYNAME = "spl-cascaded-oe-selftest"
624 SPL_MKIMAGE_SIGN_ARGS = "-c 'a smart cascaded U-Boot comment'"
687 'key-name-hint': '"spl-cascaded-oe-selftest"',
718 …self.assertEqual(value, 'sha256,rsa2048:spl-cascaded-oe-selftest', 'Signature algorithm for %s not…
/openbmc/linux/arch/mips/include/asm/
H A Di8259.h68 * Interrupt is cascaded so perform interrupt in i8259_irq()
/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.h41 * Offset DPCD 050Eh == 0x5A indicates cascaded MST hub case
/openbmc/linux/arch/mips/dec/
H A Dioasic-irq.c82 * ASIC is cascaded to, are level-triggered it is recommended that error

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