| /openbmc/entity-manager/docs/ |
| H A D | blacklist_configuration.md | 3 The blacklist.json in package directory can determine i2c buses and addresses
8 ## For buses
10 Put in numbers of buses. For example:
14 "buses": [1, 3, 5]
18 Note that "buses" should be an array of unsigned integer.
26 "buses": [
46 "buses": [
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| /openbmc/u-boot/drivers/i2c/muxes/ |
| H A D | Kconfig | 5 This enables I2C buses to be multiplexed, so that you can select
6 one of several buses using some sort of control mechanism. The
14 This enables I2C buses to be multiplexed, so that you can select
15 one of several buses using some sort of control mechanism. The
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| /openbmc/linux/drivers/net/mdio/ |
| H A D | Kconfig | 79 tristate "Bitbanged MDIO buses"
109 tristate "GPIO lib-based bitbanged MDIO buses"
160 tristate "Octeon and some ThunderX SOCs MDIO buses"
167 buses. It is required by the Octeon and ThunderX ethernet device
200 tristate "ThunderX SOCs MDIO buses"
251 child MDIO bus to a parent bus. Buses could be internal as well as
262 child MDIO bus to a parent bus. Buses could be internal as well as
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| H A D | mdio-thunder.c | 19 struct cavium_mdiobus *buses[4]; member
84 nexus->buses[i] = bus; in thunder_mdiobus_pci_probe()
106 if (i >= ARRAY_SIZE(nexus->buses)) in thunder_mdiobus_pci_probe()
125 for (i = 0; i < ARRAY_SIZE(nexus->buses); i++) { in thunder_mdiobus_pci_remove()
126 struct cavium_mdiobus *bus = nexus->buses[i]; in thunder_mdiobus_pci_remove()
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| /openbmc/u-boot/doc/ |
| H A D | README.bitbangMII | 2 support an arbitrary number of mii buses. This feature is useful when your
3 board uses different mii buses for different phys and all (or a part) of these
4 buses are implemented via bit-banging mode.
29 the bb_miiphy_buses_num variable with the number of mii buses.
|
| /openbmc/linux/drivers/pci/ |
| H A D | probe.c | 1231 * pci_scan_bridge_extend() - Scan buses behind a bridge
1234 * @max: Starting subordinate number of buses behind this bridge
1235 * @available_buses: Total number of buses available for this bridge and
1237 * been allocated the remaining buses will be
1248 * them, we proceed to assigning numbers to the remaining buses in
1251 * Return: New subordinate number covering all buses behind this bridge.
1259 u32 buses, i, j = 0; in pci_scan_bridge_extend() local
1273 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); in pci_scan_bridge_extend()
1274 primary = buses & 0xFF; in pci_scan_bridge_extend()
1275 secondary = (buses >> in pci_scan_bridge_extend()
1307 unsigned int cmax, buses; pci_scan_bridge_extend() local
2967 unsigned int buses = 0; pci_scan_child_bus_extend() local
[all...] |
| H A D | pci-bridge-emul.h | 144 * requests between primary and secondary buses.
150 * primary and secondary buses.
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| /openbmc/linux/sound/i2c/ |
| H A D | i2c.c | 46 list_del(&bus->buses); in snd_i2c_bus_free()
48 while (!list_empty(&bus->buses)) { in snd_i2c_bus_free()
49 slave = snd_i2c_slave_bus(bus->buses.next); in snd_i2c_bus_free()
80 INIT_LIST_HEAD(&bus->buses); in snd_i2c_bus_create()
84 list_add_tail(&bus->buses, &master->buses); in snd_i2c_bus_create()
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| /openbmc/linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | fsl,imx8m-noc.yaml | 13 The i.MX SoC family has multiple buses for which clock frequency (and
16 Some of those buses expose register areas mentioned in the memory maps as GPV
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
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| /openbmc/linux/include/sound/ |
| H A D | i2c.h | 45 struct list_head buses; /* master: slave buses sharing SCK/SCL, slave: link list */ member
60 #define snd_i2c_slave_bus(n) list_entry(n, struct snd_i2c_bus, buses)
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| /openbmc/linux/drivers/net/can/softing/ |
| H A D | Kconfig | 8 Softing Gmbh CAN cards come with 1 or 2 physical buses.
15 controls the 2 buses on the card together.
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| /openbmc/qemu/docs/system/ |
| H A D | device-emulation.rst | 29 Device Buses
33 machine model you choose (``-M foo``) a number of buses will have been
42 additional buses to the system that other devices can be attached to.
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| /openbmc/linux/include/linux/amba/ |
| H A D | pl08x.h | 54 * these buses (use PL08X_AHB1 | PL08X_AHB2).
101 * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
102 * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
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| /openbmc/linux/drivers/cdx/controller/ |
| H A D | mcdi_functions.h | 15 * cdx_mcdi_get_num_buses - Get the total number of buses on
19 * Return: total number of buses available on the controller,
|
| /openbmc/openbmc/meta-ingrasys/meta-zaius/recipes-phosphor/chassis/avsbus-control/ |
| H A D | zaius_avsbus.sh | 9 buses="$cpu0_i2c_bus $cpu1_i2c_bus"
40 for bus in $buses
|
| /openbmc/u-boot/doc/device-tree-bindings/net/ |
| H A D | fsl-tsec-phy.txt | 48 This PHY is accessed through the local MDIO bus. These buses are defined
49 similarly to the mdio buses. The TBI PHYs underneath them are similar to
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| /openbmc/linux/Documentation/devicetree/bindings/gnss/ |
| H A D | sirfstar.yaml | 20 SiRF chips can be used over UART, I2C or SPI buses.
38 The I2C Address, SPI chip select address. Not required on UART buses.
|
| /openbmc/qemu/docs/ |
| H A D | pcie_pci_bridge.txt | 29 any device plugged in, has no free buses reserved to provide any of them
32 To solve this problem we reserve additional buses on a firmware level.
49 uint32_t bus_res; Minimum number of buses to reserve
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| /openbmc/linux/Documentation/mhi/ |
| H A D | mhi.rst | 14 speed peripheral buses or shared memory. Even though MHI can be easily adapted
15 to any peripheral buses, it is primarily used with PCIe based devices. MHI
16 provides logical channels over the physical buses and allows transporting the
29 which are mapped to the host memory space by the peripheral buses like PCIe.
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | cavium-mdio.txt | 35 Several mdio buses may be gathered as children of a single PCI
36 device, this PCI device is the nexus of the buses.
|
| H A D | fsl-tsec-phy.txt | 40 This PHY is accessed through the local MDIO bus. These buses are defined
41 similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi".
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| /openbmc/linux/Documentation/driver-api/media/ |
| H A D | v4l2-intro.rst | 14 more I2C buses, but other buses can also be used. Such devices are
|
| /openbmc/entity-manager/src/ |
| H A D | fru_device.cpp | 185 return; // the mux buses are random, no need to publish in makeProbeInterface()
585 // It's expected to have at least one field, "buses" that is an array of the in loadBlocklist()
586 // buses by integer. Allow for future options to exclude further aspects, in loadBlocklist()
594 // If buses field is missing, that's fine. in loadBlocklist()
595 if (data.count("buses") == 1) in loadBlocklist()
597 // Parse the buses array after a little validation. in loadBlocklist()
598 auto buses = data.at("buses"); in loadBlocklist() local
599 if (buses.type() != nlohmann::json::value_t::array) in loadBlocklist()
601 // Buses field present but invalid, therefore this is an error. in loadBlocklist()
602 std::cerr << "Invalid contents for blocklist buses field\n"; in loadBlocklist()
[all …]
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| /openbmc/qemu/docs/devel/ |
| H A D | kconfig.rst | 16 Each QEMU target enables a subset of the boards, devices and buses that
141 **subsystems**, of which **buses** are a special case
153 subsystems or buses. For example, ``AUX`` (the DisplayPort auxiliary
172 have no ``depends on`` directive. Devices also *select* the buses
|
| /openbmc/linux/Documentation/driver-api/hte/ |
| H A D | hte.rst | 13 monitor sets of system signals, lines, buses etc... in realtime for state
67 lines, GPIO, chip signals, buses etc...
|