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/openbmc/qemu/include/qemu/
H A Dthrottle-options.h7 * See the COPYING file in the top-level directory for details.
13 #define QEMU_OPT_IOPS_TOTAL "iops-total"
14 #define QEMU_OPT_IOPS_TOTAL_MAX "iops-total-max"
15 #define QEMU_OPT_IOPS_TOTAL_MAX_LENGTH "iops-total-max-length"
16 #define QEMU_OPT_IOPS_READ "iops-read"
17 #define QEMU_OPT_IOPS_READ_MAX "iops-read-max"
18 #define QEMU_OPT_IOPS_READ_MAX_LENGTH "iops-read-max-length"
19 #define QEMU_OPT_IOPS_WRITE "iops-write"
20 #define QEMU_OPT_IOPS_WRITE_MAX "iops-write-max"
21 #define QEMU_OPT_IOPS_WRITE_MAX_LENGTH "iops-write-max-length"
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dqcom_hidma_mgmt.txt14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
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H A Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
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/openbmc/u-boot/drivers/sysreset/
H A Dsysreset_mpc83xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
62 "TDM-DMAC"
70 "Address-only, Clean Block",
71 "Address-only, lwarx reservation set",
72 "Single-beat or Burst write",
74 "Address-only, Flush Block",
76 "Burst write",
78 "Address-only, sync",
79 "Address-only, tlbsync",
80 "Single-beat or Burst read",
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/openbmc/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
36 u32 cs_rd_off; /* Read deassertion time */
41 u32 adv_rd_off; /* Read deassertion time */
44 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
59 u32 access; /* Start-cycle to first data valid delay */
60 u32 rd_cycle; /* Total read cycle time */
95 u32 t_rd_cycle; /* read cycle time */
96 u32 t_cez_r; /* read CS deassertion to high Z */
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/openbmc/linux/samples/pktgen/
H A Dpktgen_sample03_burst_single_flow.sh2 # SPDX-License-Identifier: GPL-2.0
5 # - If correctly tuned[1], single CPU 10G wirespeed small pkts is possible[2]
7 # Using pktgen "burst" option (use -b $N)
8 # - To boost max performance
9 # - Avail since: kernel v3.18
10 # * commit 38b2cf2982dc73 ("net: pktgen: packet bursting via skb->xmit_more")
11 # - This avoids writing the HW tailptr on every driver xmit
12 # - The performance boost is impressive, see commit and blog [2]
19 # [1] http://netoptimizer.blogspot.dk/2014/06/pktgen-for-network-overload-testing.html
20 # [2] http://netoptimizer.blogspot.dk/2014/10/unlocked-10gbps-tx-wirespeed-smallest.html
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H A Dpktgen_sample05_flow_per_thread.sh2 # SPDX-License-Identifier: GPL-2.0
4 # Script will generate one flow per thread (-t N)
5 # - Same destination IP
6 # - Fake source IPs for each flow (fixed based on thread number)
10 # separate-flow should not access shared variables/data. This script
24 if [ -z "$DEST_IP" ]; then
25 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1"
27 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
28 [ -z "$CLONE_SKB" ] && CLONE_SKB="0"
29 [ -z "$BURST" ] && BURST=32
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H A Dpktgen_bench_xmit_mode_netif_receive.sh2 # SPDX-License-Identifier: GPL-2.0
5 # - developed for benchmarking ingress qdisc path
16 # ------------------------------------------------------------------
24 # (3) ingress on this dev, handle_ing() -> tc_classify()
42 if [ -z "$DEST_IP" ]; then
43 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1"
45 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
46 [ -z "$BURST" ] && BURST=1024
47 [ -z "$COUNT" ] && COUNT="10000000" # Zero means indefinitely
48 if [ -n "$DEST_IP" ]; then
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/openbmc/u-boot/drivers/tpm/
H A Dtpm_tis_lpc.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <tpm-v1.h>
87 /* Retrieve burst count value out of the status register contents. */
98 debug(PREFIX "Read reg 0x%4.4x returns 0x%2.2x\n", in tpm_read_byte()
99 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, ret); in tpm_read_byte()
106 debug(PREFIX "Read reg 0x%4.4x returns 0x%8.8x\n", in tpm_read_word()
107 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, ret); in tpm_read_word()
114 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, value); in tpm_write_byte()
122 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, value); in tpm_write_word()
132 * @reg - pointer to the TPM register
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/openbmc/linux/drivers/char/tpm/
H A Dtpm_tis_i2c_cr50.c1 // SPDX-License-Identifier: GPL-2.0
10 * - Use an interrupt for transaction status instead of hardcoded delays.
11 * - Must use write+wait+read read protocol.
12 * - All 4 bytes of status register must be read/written at once.
13 * - Burst count max is 63 bytes, and burst count behaves slightly differently
15 * - When reading from FIFO the full burstcnt must be read instead of just
45 * struct tpm_i2c_cr50_priv_data - Driver private data.
60 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler.
74 struct tpm_i2c_cr50_priv_data *priv = dev_get_drvdata(&chip->dev); in tpm_cr50_i2c_int_handler()
76 complete(&priv->tpm_ready); in tpm_cr50_i2c_int_handler()
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/openbmc/qemu/hw/ssi/
H A Dimx_spi.c4 * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
7 * See the COPYING file in the top-level directory.
76 fifo32_reset(&s->tx_fifo); in imx_spi_txfifo_reset()
77 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE; in imx_spi_txfifo_reset()
78 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF; in imx_spi_txfifo_reset()
83 fifo32_reset(&s->rx_fifo); in imx_spi_rxfifo_reset()
84 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR; in imx_spi_rxfifo_reset()
85 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF; in imx_spi_rxfifo_reset()
86 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO; in imx_spi_rxfifo_reset()
93 if (fifo32_is_empty(&s->rx_fifo)) { in imx_spi_update_irq()
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
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H A Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
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/openbmc/linux/drivers/dma/qcom/
H A Dhidma_mgmt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
22 #include <linux/dma-mapping.h>
50 "maximum write burst (default: ACPI/DT value)");
55 "maximum read burst (default: ACPI/DT value)");
65 "maximum number of read transactions (default: ACPI/DT value)");
72 if (!is_power_of_2(mgmtdev->max_write_request) || in hidma_mgmt_setup()
73 (mgmtdev->max_write_request < 128) || in hidma_mgmt_setup()
74 (mgmtdev->max_write_request > 1024)) { in hidma_mgmt_setup()
75 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", in hidma_mgmt_setup()
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/openbmc/linux/include/linux/iio/imu/
H A Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
26 * struct adis_timeouts - ADIS chip variant timeouts
27 * @reset_ms - Wait time after rst pin goes inactive
28 * @sw_reset_ms - Wait time after sw reset command
29 * @self_test_ms - Wait time after self test command
38 * struct adis_data - ADIS chip variant specific data
39 * @read_delay: SPI delay for read operations in us
47 * @self_test_mask: Bitmask of supported self-test operations
49 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
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/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
46 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
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/openbmc/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
H A Ddma_public.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 /*! Read the control registers of DMA[ID]
47 /*! Read from a control register of DMA[ID]
59 /*! Set maximum burst size of DMA[ID]
62 \param conn[in] Connection to set max burst size for
63 \param max_burst_size[in] Maximum burst size in words
/openbmc/linux/arch/sparc/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
46 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
50 #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
55 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
56 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
57 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
58 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
62 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
66 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
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/openbmc/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
23 /* Enable bit for Host Burst Access */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
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/openbmc/linux/tools/testing/selftests/drivers/net/netdevsim/
H A Ddevlink_trap.sh2 # SPDX-License-Identifier: GPL-2.0
4 # This test is for checking devlink-trap functionality. It makes use of
40 if [ ! -d "$NETDEVSIM_PATH" ]; then
45 if [ -d "${NETDEVSIM_PATH}/devices/netdevsim${DEV_ADDR}" ]; then
54 if [ $((state & 1)) -ne 0 ]; then
65 test $(devlink_traps_num_get) -ne 0
80 # The action of non-drop traps cannot be changed.
137 check_fail $? "Did not get an error for non-existing trap"
139 log_test "Non-existing trap"
154 check_fail $? "Did not get an error for non-existing trap action"
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/openbmc/linux/include/linux/mtd/
H A Dhyperbus.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
18 #define HYPERBUS_BT 0x20 /* Burst Type */
28 * struct hyperbus_device - struct representing HyperBus slave device
47 * struct hyperbus_ops - struct representing custom HyperBus operations
48 * @read16: read 16 bit of data from flash in a single burst. Used to read
50 * @write16: write 16 bit of data to flash in a single burst. Used to
69 * struct hyperbus_ctlr - struct representing HyperBus controller
82 * hyperbus_register_device - probe and register a HyperBus slave memory device
90 * hyperbus_unregister_device - deregister HyperBus slave memory device
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dcpu_init.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
12 #include <usb/ehci-ci.h>
211 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); in cpu_init_f()
213 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); in cpu_init_f()
215 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); in cpu_init_f()
217 /* RSR - Reset Status Register - clear all status (4.6.1.3) */ in cpu_init_f()
218 gd->arch.reset_status = __raw_readl(&im->reset.rsr); in cpu_init_f()
219 __raw_writel(~(RSR_RES), &im->reset.rsr); in cpu_init_f()
221 /* AER - Arbiter Event Register - store status */ in cpu_init_f()
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/openbmc/linux/drivers/ata/
H A Dahci_ceva.c1 // SPDX-License-Identifier: GPL-2.0-only
73 #define DRV_NAME "ahci-ceva"
78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
124 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()
125 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()
141 * Set Mem Addr Read, Write ID for data transfers in ahci_ceva_setup()
142 * Set Mem Addr Read ID, Write ID for non-data transfers in ahci_ceva_setup()
150 if (cevapriv->is_cci_enabled) { in ahci_ceva_setup()
164 writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C); in ahci_ceva_setup()
167 writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C); in ahci_ceva_setup()
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos_mipi_dsi.txt1 Exynos MIPI-DSIM Controller
6 compatible: should be "samsung,exynos-mipi-dsi"
7 reg: Base address of MIPI-DSIM IP.
10 samsung,dsim-config-e-interface: interface to be used (RGB interface
12 samsung,dsim-config-e-virtual-ch: virtual channel number that main
14 samsung,dsim-config-e-pixel-format: pixel stream format for main
16 samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
17 in Non-burst mode, RGB data area is filled with RGB data and
19 samsung,dsim-config-e-no-data-lane: data lane count used by Master.
20 samsung,dsim-config-e-byte-clk: select byte clock source.
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