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/openbmc/qemu/include/qemu/
H A Dthrottle-options.h7 * See the COPYING file in the top-level directory for details.
13 #define QEMU_OPT_IOPS_TOTAL "iops-total"
14 #define QEMU_OPT_IOPS_TOTAL_MAX "iops-total-max"
15 #define QEMU_OPT_IOPS_TOTAL_MAX_LENGTH "iops-total-max-length"
16 #define QEMU_OPT_IOPS_READ "iops-read"
17 #define QEMU_OPT_IOPS_READ_MAX "iops-read-max"
18 #define QEMU_OPT_IOPS_READ_MAX_LENGTH "iops-read-max-length"
19 #define QEMU_OPT_IOPS_WRITE "iops-write"
20 #define QEMU_OPT_IOPS_WRITE_MAX "iops-write-max"
21 #define QEMU_OPT_IOPS_WRITE_MAX_LENGTH "iops-write-max-length"
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/openbmc/u-boot/drivers/sysreset/
H A Dsysreset_mpc83xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
62 "TDM-DMAC"
70 "Address-only, Clean Block",
71 "Address-only, lwarx reservation set",
72 "Single-beat or Burst write",
74 "Address-only, Flush Block",
76 "Burst write",
78 "Address-only, sync",
79 "Address-only, tlbsync",
80 "Single-beat or Burst read",
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/openbmc/qemu/hw/ssi/
H A Dimx_spi.c4 * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
7 * See the COPYING file in the top-level directory.
76 fifo32_reset(&s->tx_fifo); in imx_spi_txfifo_reset()
77 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE; in imx_spi_txfifo_reset()
78 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF; in imx_spi_txfifo_reset()
83 fifo32_reset(&s->rx_fifo); in imx_spi_rxfifo_reset()
84 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR; in imx_spi_rxfifo_reset()
85 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF; in imx_spi_rxfifo_reset()
86 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO; in imx_spi_rxfifo_reset()
93 if (fifo32_is_empty(&s->rx_fifo)) { in imx_spi_update_irq()
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/openbmc/u-boot/drivers/tpm/
H A Dtpm_tis_lpc.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <tpm-v1.h>
87 /* Retrieve burst count value out of the status register contents. */
98 debug(PREFIX "Read reg 0x%4.4x returns 0x%2.2x\n", in tpm_read_byte()
99 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, ret); in tpm_read_byte()
106 debug(PREFIX "Read reg 0x%4.4x returns 0x%8.8x\n", in tpm_read_word()
107 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, ret); in tpm_read_word()
114 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, value); in tpm_write_byte()
122 (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, value); in tpm_write_word()
132 * @reg - pointer to the TPM register
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H A DKconfig46 bool "Enable I2C burst length limitation"
58 Use this to set the burst limitation length
74 TCG Main Specification 1.2. OIAP-authorised versions of the commands
81 ---help---
90 ---help---
136 such as basic configuration, PCR extension and PCR read. Extended
H A Dtpm2_tis_core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on the Linux TIS core interface and U-Boot original SPI TPM driver
10 #include <tpm-v2.h>
20 return -ENOSPC; in tpm_tis_get_desc()
24 dev->name, chip->vend_dev & 0xFFFF, in tpm_tis_get_desc()
25 chip->vend_dev >> 16, chip->rid, in tpm_tis_get_desc()
26 (chip->is_open ? "open" : "closed")); in tpm_tis_get_desc()
30 * tpm_tis_check_locality - Check the current TPM locality
40 struct tpm_tis_phy_ops *phy_ops = chip->phy_ops; in tpm_tis_check_locality()
43 phy_ops->read_bytes(dev, TPM_ACCESS(loc), 1, &locality); in tpm_tis_check_locality()
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos_mipi_dsi.txt1 Exynos MIPI-DSIM Controller
6 compatible: should be "samsung,exynos-mipi-dsi"
7 reg: Base address of MIPI-DSIM IP.
10 samsung,dsim-config-e-interface: interface to be used (RGB interface
12 samsung,dsim-config-e-virtual-ch: virtual channel number that main
14 samsung,dsim-config-e-pixel-format: pixel stream format for main
16 samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
17 in Non-burst mode, RGB data area is filled with RGB data and
19 samsung,dsim-config-e-no-data-lane: data lane count used by Master.
20 samsung,dsim-config-e-byte-clk: select byte clock source.
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/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dcpu_init.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
12 #include <usb/ehci-ci.h>
211 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); in cpu_init_f()
213 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); in cpu_init_f()
215 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); in cpu_init_f()
217 /* RSR - Reset Status Register - clear all status (4.6.1.3) */ in cpu_init_f()
218 gd->arch.reset_status = __raw_readl(&im->reset.rsr); in cpu_init_f()
219 __raw_writel(~(RSR_RES), &im->reset.rsr); in cpu_init_f()
221 /* AER - Arbiter Event Register - store status */ in cpu_init_f()
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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
22 - clock-names: May contain any/all of the following depending on the IP
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/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
39 # bit11-7: 0 required
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/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
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H A Dkwbimage-lsxhl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
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/openbmc/qemu/util/
H A Dthrottle.c4 * Copyright (C) Nodalink, EURL. 2013-2014
41 leak = (bkt->avg * (double) delta_ns) / NANOSECONDS_PER_SECOND; in throttle_leak_bucket()
44 bkt->level = MAX(bkt->level - leak, 0); in throttle_leak_bucket()
47 * keep track of bkt->burst_level so the bkt->max goal per second in throttle_leak_bucket()
49 if (bkt->burst_length > 1) { in throttle_leak_bucket()
50 leak = (bkt->max * (double) delta_ns) / NANOSECONDS_PER_SECOND; in throttle_leak_bucket()
51 bkt->burst_level = MAX(bkt->burst_level - leak, 0); in throttle_leak_bucket()
62 int64_t delta_ns = now - ts->previous_leak; in throttle_do_leak()
65 ts->previous_leak = now; in throttle_do_leak()
73 throttle_leak_bucket(&ts->cfg.buckets[i], delta_ns); in throttle_do_leak()
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/openbmc/u-boot/arch/arm/dts/
H A Domap3-igep.dtsi11 /dts-v1/;
22 stdout-path = &uart3;
26 compatible = "ti,omap-twl4030";
31 vdd33: regulator-vdd33 {
32 compatible = "regulator-fixed";
33 regulator-name = "vdd33";
34 regulator-always-on;
41 pinctrl-single,pins = <
48 pinctrl-single,pins = <
55 pinctrl-single,pins = <
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/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Low-level initialization for EP93xx
17 #include <asm/arch-ep93xx/ep93xx.h>
22 * Input: r0 - SDRAM DEVCFG register
23 * r2 - configuration for SDRAM chips
85 /* Program the mode register on the SDRAM by performing fake read */
98 * Input: r0 - Test address of SDRAM
99 * Output: r0 - 0 -- Test OK, -1 -- Failed
100 * Modifies: r0-r5
110 stmia r0, {r1-r4}
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/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32-fmc.txt3 - compatible : "st,stm32-fmc"
4 - reg : fmc controller base address
5 - clocks : fmc controller clock
6 u-boot,dm-pre-reloc: flag to initialize memory before relocation.
8 on-board sdram memory attributes:
9 - st,sdram-control : parameters for sdram configuration, in this order:
15 read burst enable or disable
16 read pipe delay
18 - st,sdram-timing: timings for sdram, in this order:
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
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/openbmc/u-boot/drivers/rtc/
H A Dds1302.c2 * ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip
34 while (num--) printf("%x ", *ptr++); in DUMP()
55 unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */
155 DPRINTF("READ 0x%x bytes @ 0x%x [ ", count, addr); in read_ser_drv()
157 addr|=1; /* READ */ in read_ser_drv()
208 /* read burst */ in rtc_init()
227 bbclk.year10=100/10; /* 2000 - why not? ;) */ in rtc_init()
262 read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* read burst */ in rtc_get()
267 rel = -1; in rtc_get()
270 tmp->tm_sec=10*bbclk.sec10+bbclk.sec; in rtc_get()
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/openbmc/u-boot/board/cssi/MCR3000/
H A DMCR3000.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2017 CS Systemes d'Information
4 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
5 * Christophe Leroy <christophe.leroy@c-s.fr>
23 /* DRAM - single read. (offset 0 in upm RAM) */
27 /* DRAM - burst read. (offset 8 in upm RAM) */
33 /* DRAM - single write. (offset 18 in upm RAM) */
37 /* DRAM - burst write. (offset 20 in upm RAM) */
61 do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", in ft_board_setup()
62 bd->bi_busfreq, 1); in ft_board_setup()
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/openbmc/u-boot/drivers/misc/
H A Dcros_ec.c1 // SPDX-License-Identifier: GPL-2.0+
28 #include <asm-generic/gpio.h>
29 #include <dm/device-internal.h>
31 #include <dm/uclass-internal.h>
100 if (cmd != -1) in cros_ec_dump_data()
109 * Calculate a simple 8-bit checksum of a data block
129 * @param dev CROS-EC device
140 struct ec_host_request *rq = (struct ec_host_request *)cdev->dout; in create_proto3_request()
144 if (out_bytes > (int)sizeof(cdev->dout)) { in create_proto3_request()
146 return -EC_RES_REQUEST_TRUNCATED; in create_proto3_request()
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/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
80 #define ACFG_SDRAM_W2R_DELAY 1 /* write to read
90 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
91 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
103 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
108 * 0 = Burst mode
126 #define ACFG_SDRAM_W2R_DELAY 1 /* write to read
136 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
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/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dmipi_dsim.h1 /* SPDX-License-Identifier: GPL-2.0+ */
62 /* MIPI DSI Processor-to-Peripheral transaction types */
111 * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
138 * @e_burst_mode: selects Burst mode in Video mode.
139 * in Non-burst mode, RGB data area is filled with RGB data and NULL
141 * In Burst mode, RGB data area is filled with RGB data only.
152 * read packet(or write "set_tear_on" command) and BTA request.
153 * after transmitting read packet or write "set_tear_on" command,
154 * BTA requests to D-PHY automatically. this counter value specifies
162 * - RxValid specifies Rx data valid indicator.
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/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
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/openbmc/qemu/docs/
H A Dthrottle.txt7 later. See the COPYING file in the top-level directory.
10 ------------
21 ----------------------------------
24 them the user can set a global limit or separate limits for read and
27 I/O limits can be set using the throttling.* parameters of -drive, or
31 |-----------------------+-----------------------|
32 | -drive | block_set_io_throttle |
33 |-----------------------+-----------------------|
34 | throttling.iops-total | iops |
35 | throttling.iops-read | iops_rd |
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